AD7225 데이터 시트보기 (PDF) - Analog Devices
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AD7225 Datasheet PDF : 24 Pages
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AD7225
INTERFACE LOGIC INFORMATION
The AD7225 contains two registers per DAC, an input register
LDAC
TO ALL
DAC LATCHES
and a DAC register. The A0 and A1 address lines select which
A0
input register accepts data from the input port. When the WR
TO INPUT
LATCH A
signal is low, the input latches of the selected DAC are transpa-
A1
rent. The data is latched into the addressed input register on the
rising edge of WR. Table 5 shows the addressing for the input
TO INPUT
LATCH B
TO INPUT
LATCH C
registers on the AD7225.
Table 5. AD7225 Addressing
A1
A0
Selected Input Register
TO INPUT
LATCH D
WR
Figure 12. Input Control Logic
Low
Low
DAC A
Low
High
High
High
Low
High
DAC B
DAC C
DAC D
Only the data held in the DAC register determines the analog
output of the converter. The LDAC signal is common to all four
DACs and controls the transfer of information from the input
registers to the DAC registers. Data is latched into all four DAC
registers simultaneously on the rising edge of LDAC. The LDAC
signal is level triggered and therefore the DAC registers can be
made transparent by tying LDAC low (in this case, the outputs
of the converters respond to the data held in their respective
input latches). LDAC is an asynchronous signal and is indepen-
dent of WR. This is useful in many applications. However, in
5V
ADDRESS
VINH
VINL
0V
t2
t3
t1
5V
WR
LDAC
t5
t4
t6
5V
5V
DATA IN
DATA
VALID
0V
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM
10% TO 90% OF 5V.
tR = tF = 20ns OVER VDD RANGE.
2. TIMING MEASUREMENT REFERENCE LEVEL IS
VINH + VINL
2
systems where the asynchronous LDAC can occur during a
write cycle (or vice versa), care must be taken to ensure that
3. IF LDAC IS ACTIVATED PRIOR TO THE RISING EDGE OF WR,
THEN IT MUST STAY LOW FOR t6 OR LONGER AFTER WR
GOES HIGH.
incorrect data is not latched through to the output. If LDAC is
Figure 13. Write Cycle Timing Diagram
activated prior to the rising edge of WR (or WR occurs during
LDAC), LDAC must stay low for t6 or longer after WR goes high
to ensure correct data is latched through to the output. Table 6
shows the truth table for AD7225 operation. Figure 12 shows
the input control logic for the part; the write cycle timing
diagram is given in Figure 13.
Table 6. Truth Table
WR LDAC Function
High High No operation. Device not selected.
Low High Input register of selected DAC transparent.
High Input register of selected DAC latched.
High Low
All four DAC registers Transparent (that is,
outputs respond to data held in respective
input registers). Input registers are latched.
High
All four DAC registers latched.
Low Low
DAC registers and selected input register
transparent output follows input data for
selected channel.
Rev. C | Page 10 of 24
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