AD7228A 데이터 시트보기 (PDF) - Analog Devices
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AD7228A Datasheet PDF : 8 Pages
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AD7228A–SPECIFICATIONS
DUAL SUPPLY (VDD = 10.8 V to 16.5 V; VSS = –5 V ؎ 10%; GND = 0 V; VREF = +2 V to +10 V1; RL = 2 kΩ, CL = 100 pF unless otherwise
noted.) All specifications TMIN to TMAX unless otherwise noted.
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error3
Relative Accuracy
Differential Nonlinearity
Full-Scale Error4
Zero Code Error
@ 25°C
TMIN to TMAX
Minimum Load Resistance
REFERENCE INPUT
Voltage Range1
Input Resistance
Input Capacitance5
AC Feedthrough
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance5
Input Coding
DYNAMIC PERFORMANCE5
Voltage Output Slew Rate
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Digital Crosstalk6
POWER SUPPLIES
VDD Range
VSS Range
IDD
@ 25°C
TMIN to TMAX
ISS
@ 25°C
TMIN to TMAX
B
Version2
8
±2
±1
±1
±1
± 25
± 30
2
2 to 10
2
500
–70
2.4
0.8
±1
8
Binary
2
5
5
50
50
10.8/16.5
–4.5/–5.5
16
20
14
18
C
T
U
Version Version Version
8
8
8
±1
±2
±1
± 1/2
±1
± 1/2
±1
±1
±1
± 1/2
±1
± 1/2
± 15
± 25
± 15
± 20
± 30
± 20
2
2
2
2 to 10
2
500
–70
2 to 10
2
500
–70
2 to 10
2
500
–7 0
2.4
0.8
±1
8
Binary
2.4
0.8
±1
8
Binary
2.4
0.8
±1
8
Binary
2
2
2
5
5
5
5
5
5
50
50
50
50
50
50
10.8/16.5 10.8/16.5 10.8/16.5
–4.5/–5.5 –4.5/–5.5 –4.5/–5.5
16
16
16
20
22
22
14
14
14
18
20
20
Units
Bits
LSB max
LSB max
LSB max
LSB max
mV max
mV max
kΩ min
V min/V max
kΩ min
pF max
dB typ
V min
V max
µA max
pF max
V/µs min
µs max
µs max
nV secs typ
nV secs typ
V min/V max
V min/V max
mA max
mA max
mA max
mA max
Conditions/Comments
VDD = +15 V ± 10%, VREF = +10 V
Guaranteed Monotonic
Typical tempco is 5 ppm/°C with VREF = +10 V
Typical tempco is 30 µV/°C
VOUT = +10 V
Occurs when each DAC is loaded with all 1s.
VREF = 8 V p-p Sine Wave @ 10 kHz
VIN = 0 V or VDD
VREF = +10 V; Settling Time to ± 1/2 LSB
VREF = +10 V; Settling Time to ± 1/2 LSB
Code transition all 0s to all 1s. VREF = 0 V; WR = VDD
Code transition all 0s to all 1s. VREF = +10 V; WR = 0 V
For Specified Performance
For Specified Performance
Outputs Unloaded; VIN = VINL or VINH
Outputs Unloaded; VIN = VINL or VINH
SINGLE SUPPLY (VDD = +15 V ؎ 10%, VSS; = GND = 0 V; VREF = +10 V, RL = 2 kΩ, CL = 100 pF unless otherwise noted.)
AII specifications TMIN to TMAX unless otherwise noted.
STATIC PERFORMANCE
Resolution
8
Total Unadjusted Error3
±2
Differential Nonlinearity
±1
Minimum Load Resistance
2
REFERENCE INPUT
Input Resistance
2
Input Capacitance5
500
8
8
8
±1
±2
±1
±1
±1
±1
2
2
2
2
2
2
500
500
500
Bits
LSB max
LSB max
kΩ min
kΩ min
pF max
Guaranteed Monotonic
VOUT = +10 V
Occurs when each DAC is loaded with all 1s.
DIGITAL INPUTS
As per Dual Supply Specifications
DYNAMIC PERFORMANCE5
Voltage Output Slew Rate
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Digital Crosstalk6
POWER SUPPLIES
VDD Range
IDD
@ 25°C
TMIN to TMAX
2
5
7
50
50
13.5/16.5
16
20
2
2
2
5
5
5
7
7
7
50
50
50
50
50
50
13.5/16.5 13.5/16.5 13.5/16.5
16
16
16
20
22
22
V/µs min
µs max
µs max
nV secs typ
nV secs typ
V min/V max
mA max
mA max
Settling Time to ± 1/2 LSB
Settling Time to ± 1/2 LSB
Code transition all 0s to all 1s. VREF = 0 V; WR = VDD
Code transition all 0s to all 1s. VREF = +10 V, WR = 0 V
For Specified Performance
Outputs Unloaded; VIN = VINL or VINH
NOTES
1VOUT must be less than VDD by 3.5 V to ensure correct operation.
2Temperature ranges are as follows:
B, C Versions; –40°C to +85°C
T, U Versions; –55°C to +125°C
3Total Unadjusted Error includes zero code error, relative accuracy and full-scale error.
4Calculated after zero code error has been adjusted out.
5Sample tested at 25°C to ensure compliance.
6The glitch impulse transferred to the output of one converter (not addressed) due to a
change in the digital input code to another addressed converter.
Specifications subject to change without notice.
–2–
REV. A
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