AD7298BCPZ-RL7(RevPrA) 데이터 시트보기 (PDF) - Analog Devices

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AD7298BCPZ-RL7
(Rev.:RevPrA)

8-Channel, 1MSPS, 12-Bit SAR ADC with Temperature Sensor

Analog Devices 

Preliminary Technical Data

POWER-DOWN MODES

The AD7298 has a number of power conservation modes of

operation, which are designed to provide flexible power

management options. These options can be chosen to optimize

the power dissipation/throughput rate ratio for different

application requirements. The power-down modes of operation

of the AD7298 is controlled by the power-down bit, in the

control register and the PD pin on the device. When power

supplies are first applied to the AD7298, care should be taken to

ensure that the part is placed in the required mode of operation

NORMAL MODE

This mode is intended for the fastest throughput rate perform-

ance because the user does not have to worry about any power-

up times with the AD7298 remaining fully powered at all times.

Figure 6 shows the general diagram of the operation of the

AD7298 in this mode. The conversion is initiated on the falling

edge of CS and the track-and-hold enters hold mode. On the14th

SCLK falling edge the track-and-hold returns to track mode

and starts acquiring the analog input, as described in the serial

interface section. The data presented to the AD7298 on the DIN

line during the first 16 clock cycles of the data transfer are

loaded into the control register (provided the WRITE bit is 1).

The part remains fully powered up in normal mode at the end

of the conversion as long as PD bit is set to 0 in the write transfer

during that conversion. To ensure continued operation in

normal mode, the PD bit should be loaded with 0 on every data

write operation. Sixteen serial clock cycles are required to

complete the conversion and access the conversion result.

For specified performance, the throughput rate should not

exceed 1MSPS. Once a conversion is complete and the CS has

returned high, a minimum of the quiet time, tQUIET, must elapse

before bringing CS low again to initiate another conversion and

access the previous conversion result.

AD7298

Figure 6. Normal Mode Operation

PARTIAL POWER DOWN MODE

In this mode, part of the internal circuitry on the AD7298 is

powered-down. The AD7298 enters partial power-down on the

CS rising edge once the current serial write operation

containing 16 SCLK clock cycles is completed. To enter partial

power-down the PD bit in the control register should be set to

one on the last required read transfer from the AD7298. Once

in partial power-down mode the AD7298 transmits all ones on

the DOUT pin if CS is toggled low. If the averaging feature for the

temperature sensor is enabled in the control register, the

averaging is reset once the device enters partial power-down

mode.

The AD7298 remains in partial power-down until the power-

down bit, PD, in the control register is changed to a logic level

zero (0). The AD7298 begins powering up on the rising edge of

CS following the write to the control register disabling the

power-down bit. Once TQUITE has elapsed, a full 16-SCLK write

to the control register must be completed to update its content

with the desired channel configuration for the subsequent

conversion. A valid conversion is then initiated on the next CS

falling edge. Since the AD7298 has once cycle latency, the first

conversion result after exiting partial power-down mode is

available in the fourth serial transfer as shown in Figure 7; 1st

cycle to update PD bit, 2nd cycle to update configuration and

Channel ID bits, 3rd to complete conversion, 4th access DOUT

valid result. The use of this mode enables a reduction in the

overall power consumption of the device.

Rev. PrA | Page 11 of 18

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