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MXED102 데이터 시트보기 (PDF) - Clare Inc => IXYS

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MXED102
Clare
Clare Inc => IXYS Clare
MXED102 Datasheet PDF : 20 Pages
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Preliminary
MXED102
Digital Inputs:
Parameter
Sym
Operating Condition
Min
Typ
Max
Input low voltage VIL
-
-
-
0.5
Input high voltage VIH
-
VCC-0.5
-
-
Input current
II
-
-10
-
10
Units
V
V
uA
Digital Outputs:
Parameter
Sym
Operating Condition
Min
Typ
Max
Output low voltage VOL
Iout = 100 uA
-
-
0.4
Output high voltage VOH
Iout = -100 uA
VCC-0.4
-
-
Output rise/fall time TRF 10 to 90 %, Cload=5 pF
-
-
2.0
Units
V
V
nS
Serial Configuration Bus:
Bus Operation:
The controller uses the serial bus to set the characteristics of all column driver ICs by writing to all column
driver ICs in parallel. During write, the controller writes the entire data packet. The controller can also inter
rogate a single column driver IC, who's MASTER pin is pulled high. Only 1 column driver IC on a given bus
can be designated as master. During read, the controller writes the preamble, start of frame delimiter, reg
ister address, and turn around bits. It then tri-states for the bus tri-state and data bits and reads the data.
Data Packet:
The data packet consists of:
- 14 bit preamble of all 1's
- 2 bit start of frame delimiter (SFD)
- 6 bit register address - MSB first
- 1 turn around bit (TA)
- 1 bus tristate (BT)
- 8 bit data packet - MSB first
Write => write data to all column driver ICs
Read => read data from master column driver IC
Data order => Preamble first, data last; MSB first, LSB last
R/W
Preamble
SFD
write 1111 1111 1111 11
00
read 1111 1111 1111 11
01
Reg Address
AAAA AA
AAAA AA
TA BT
00
0Z
Data
DDDD DDDD
DDDD DDDD
Rev. 2
www.clare.com
5

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