AD80066KRSZ(RevA) 데이터 시트보기 (PDF) - Analog Devices

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AD80066KRSZ
(Rev.:RevA)

Complete 16-Bit CCD/CIS Signal Processor

Analog Devices 

AD80066

Parameter

POWER DISSIPATION

4-Channel Mode at 24 MHz

1-Channel Mode at 12 MHz

4-Channel Mode at 8 MHz, Slow Power Mode3

Min

Typ

490

300

165

Max

Unit

mW

mW

mW

1 The linear input signal range is up to 3 V p-p when the CCD reference level is clamped to 3 V by the AD80066 input clamp (see Figure 2).

2 The PGA gain is approximately linear-in-dB but varies nonlinearly with register code (see the Programmable Gain Amplifiers (PGA) section for more information).

3 Measured with Bit D1 of the configuration register set high for 8 MHz, low power operation.

AVDD = 5V

2V TYP

RESET TRANSIENT

3V BIAS SET BY INPUT CLAMP

1.5V OR 3V p-p MAX INPUT SIGNAL RANGE

GND

Figure 2. Input Signal with the CCD Reference Level Clamped to 3 V

DIGITAL SPECIFICATIONS

TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 24 MHz, fCDSCLK1 = fCDSCLK2 = 6 MHz, CL = 10 pF, unless otherwise noted.

Table 2.

Parameter

LOGIC INPUTS

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

LOGIC OUTPUTS (DRVDD = 5 V)

High Level Output Voltage (IOH = 2 mA)

Low Level Output Voltage (IOL = 2 mA)

LOGIC OUTPUTS (DRVDD = 3 V)

High Level Output Voltage (IOH = 2 mA)

Low Level Output Voltage (IOL = 2 mA)

Symbol

VIH

VIL

IIH

IIL

CIN

VOH

VOL

VOH

VOL

Min

Typ

Max

Unit

2.0

V

0.8

V

10

μA

10

μA

10

pF

4.5

V

0.5

V

2.5

V

0.5

V

Rev. A | Page 4 of 20

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