AD80066KRSZ(RevA) 데이터 시트보기 (PDF) - Analog Devices
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AD80066KRSZ Datasheet PDF : 20 Pages
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AD80066
TIMING SPECIFICATIONS
TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V.
Table 3.
Parameter
CLOCK PARAMETERS
4-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulse Width
CDSCLK1 Pulse Width
CDSCLK2 Pulse Width
CDSCLK1 Falling1 to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Rising to ADCCLK Rising
CDSCLK2 Falling1 to ADCCLK Falling
CDSCLK2 Falling1 to CDSCLK1 Rising
Aperture Delay for CDS Clocks
SERIAL INTERFACE
Maximum SCLK Frequency, Write Operation
Maximum SCLK Frequency, Read Operation
SLOAD to SCLK Setup Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Setup Time
SCLK Rising to SDATA Hold Time
SCLK Falling to SDATA Valid
DATA OUTPUT
Output Delay
Latency (Pipeline Delay)
Symbol
tPRA
tPRB
tADCCLK
tC1
tC2
tC1C2
tADC2
tC2ADR
tC2ADF
tC2C1
tAD
fSCLK
fSCLK
tLS
tLH
tDS
tDH
tRDV
tOD
Min
166
83
20
15
15
0
0
5
20
5
50
25
5
5
2
2
10
Typ
Max
2
8
3 (fixed)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
Cycles
1 CDSCLKx falling edges should not occur within the first 10 ns following an ADCCLK edge.
Timing Diagrams
tPRA
ANALOG
INPUTS
tAD
tC1
PIXEL n (A,B,C,D)
tAD
PIXEL (n + 1)
CDSCLK1
tC2C1
tC1C2
tC2
CDSCLK2
tC2ADF
tADCCLK
tADC2
tC2ADR
ADCCLK
OUTPUT
DATA
(D[7:0])
tADCCLK
tOD
B(n – 2) C(n – 2) C(n – 2) D(n – 2) D(n – 2) A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1) D(n – 1) D(n – 1) A(n) A(n) B(n)
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW HIGH LOW HIGH LOW HIGH
BYTE BYTE BYTE BYTE BYTE BYTE
Figure 3. 4-Channel CDS Mode Timing
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
Rev. A | Page 5 of 20
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