AD80066KRSZ(RevA) 데이터 시트보기 (PDF) - Analog Devices

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AD80066KRSZ
(Rev.:RevA)

Complete 16-Bit CCD/CIS Signal Processor

Analog Devices 

AD80066

ANALOG

INPUTS

tAD

tC1

PIXEL n

tAD

tC2C1

PIXEL (n + 1)

tPRB

PIXEL (n + 2)

CDSCLK1

tC1C2

tC2

CDSCLK2

tC2ADR

tC2ADF

ADCCLK

tADCCLK

tADCCLK

tOD

OUTPUT

DATA

(D[7:0])

PIXEL (n – 4)

HIGH

BYTE

PIXEL (n – 4)

LOW

BYTE

PIXEL (n – 3)

HIGH

BYTE

PIXEL (n – 3)

LOW

BYTE

PIXEL (n – 2)

HIGH

BYTE

NOTES

1. IN 1-CHANNEL CDS MODE. THE CDSCLK1 FALLING EDGE AND THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS LOW.

Figure 6. 1-Channel CDS Mode Timing

PIXEL (n – 2)

LOW

BYTE

ANALOG

INPUTS

CDSCLK2

ADCCLK

OUTPUT

DATA

(D[7:0])

tADCCLK

PIXEL n (A, B, C, D)

tAD

tC2

tC2ADF

tADC2

tC2ADR

tPRA

PIXEL (n + 1)

tADCCLK

tOD

B(n – 2) C(n – 2) C(n – 2) D(n – 2) D(n – 2) A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1) D(n)

D(n)

A(n)

A(n)

HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW

BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE

Figure 7. 4-Channel SHA Mode Timing

Rev. A | Page 7 of 20

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