AD80066 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

제조사

AD80066

Complete 16-Bit CCD/CIS Signal Processor

Analog Devices 

Data Sheet

AD80066

ANALOG

INPUTS

tAD

tC1

PIXEL n

tAD

tC2C1

PIXEL (n + 1)

tPRB

PIXEL (n + 2)

CDSCLK1

tC1C2

tC2

CDSCLK2

tC2ADR

tC2ADF

ADCCLK

tADCCLK

tADCCLK

tOD

OUTPUT

DATA

(D[7:0])

PIXEL (n – 4)

HIGH

BYTE

PIXEL (n – 4)

LOW

BYTE

PIXEL (n – 3)

HIGH

BYTE

PIXEL (n – 3)

LOW

BYTE

PIXEL (n – 2)

HIGH

BYTE

PIXEL (n – 2)

LOW

BYTE

NOTES

1. IN 1-CHANNEL CDS MODE. THE CDSCLK1 FALLING EDGE AND THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS LOW.

Figure 6. 1-Channel CDS Mode Timing

ANALOG

INPUTS

CDSCLK2

ADCCLK

OUTPUT

DATA

(D[7:0])

tADCCLK

PIXEL n (A, B, C, D)

tAD

tC2

tC2ADF

tADC2

tC2ADR

tPRA

PIXEL (n + 1)

tADCCLK

tOD

C(n – 2) D(n – 2) D(n – 2) A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1) D(n – 1) D(n – 1) A(n)

A(n) B(n)

B(n)

HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW

BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE

Figure 7. 4-Channel SHA Mode Timing

Rev. B | Page 7 of 20

Share Link: