AD8312 데이터 시트보기 (PDF) - Analog Devices

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AD8312

50 MHz to 3.5 GHz, 45 dB RF Detector

Analog Devices 

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD8312

AD8312

VPOS 1

6 RFIN

VOUT 2

5 COMM

VSET 3

4 CFLT

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Ball No. Mnemonic Description

1

VPOS

Positive Supply Voltage (VS), 2.7 V to 5.5 V.

2

VOUT

Logarithmic Output. Output voltage increases with increasing input amplitude.

3

VSET

Setpoint Input. Connect VSET to VOUT for measurement-mode operation. The nominal logarithmic slope of

20 mV/dB can be increased to an arbitrarily high value by attenuating the signal between VOUT and VSET

(see the Increasing the Logarithmic Slope section).

4

CFLT

Connection for an External Capacitor to Slow the Response of the Output. Capacitor is connected between

CFLT and VOUT.

5

COMM

Device Common (Ground).

6

RFIN

RF Input.

Rev. 0| Page 7 of 20

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