AD8362-EVAL 데이터 시트보기 (PDF) - Analog Devices
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AD8362-EVAL Datasheet PDF : 36 Pages
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PIN CONFIGURATION AND FUNCTION DESCRIPTION
AD8362
COMM 1
16 ACOM
CHPF 2
15 VREF
DECL 3
INHI 4
INLO 5
AD8362
TOP VIEW
(Not to Scale)
14 VTGT
13 VPOS
12 VOUT
DECL 6
11 VSET
PWDN 7
10 ACOM
COMM 8
9 CLPF
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin
No. Mnemonic Description
1, 8 COMM
Common Connection. Connect via low impedance to system common.
2
CHPF
Input HPF. Connect to common via a capacitor to determine 3 dB point of input signal high-pass filter.
3, 6 DECL
Decoupling Terminals for INHI and INLO. Connect to common via a large capacitance to complete
input circuit.
4
INHI
High Signal Input Terminal. Part of a differential input port with INLO.
5
INLO
Low Signal Input Terminal. Part of a differential input port with INHI.
7
PWDN
Disable/Enable Control Input. Apply logic high voltage to shut down the AD8362.
9
CLPF
Connection for loop filter integration (averaging) capacitor, the other pin of which is usually
grounded via a resistor to improve loop stability and response time.
10, 16 ACOM
Analog Common Connection for Output Amplifier.
11 VSET
The voltage applied to this pin sets the decibel value of the required RF input voltage that results in
zero current out of CLPF and thus the loop integrating capacitor.
12 VOUT
Output of Error Amplifier. In measurement mode, normally connected directly to VSET.
13 VPOS
Connect to 5 V Power Supply.
14 VTGT
The logarithmic intercept voltage is proportional to the voltage applied to this pin. The use of a lower
target voltage increases the crest factor capacity.
15 VREF
General-Purpose Reference Voltage Output of 1.25 V (usually connected only to VTGT).
Equivalent
Circuit
Circuit A
Circuit A
Circuit B
Circuit C
Circuit D
Circuit E
Rev. B | Page 7 of 36
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