AD8465WBCPZ-R7(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD8465WBCPZ-R7
(Rev.:Rev0)

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparator

Analog Devices 

TIMING INFORMATION

Figure 2 illustrates the AD8465 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.

AD8465

LATCH ENABLE

tS

tPL

tH

DIFFERENTIAL

VIN

INPUT VOLTAGE

VOD

1.1V

VN ± VOS

Q OUTPUT

Q OUTPUT

tPDL

tPLOH

50%

tPDH

tF

50%

tR

Figure 2. System Timing Diagram

tPLOL

Table 2. Timing Descriptions

Symbol Timing

tPDH

Input-to-Output High Delay

tPDL

Input-to-Output Low Delay

tPLOH

Latch Enable-to-Output High Delay

tPLOL

Latch Enable-to-Output Low Delay

tH

Minimum Hold Time

tPL

Minimum Latch Enable Pulse Width

tS

Minimum Setup Time

tR

Output Rise Time

tF

Output Fall Time

VOD

Voltage Overdrive

Description

Propagation delay measured from the time the input signal crosses the reference (± the

input offset voltage) to the 50% point of an output low-to-high transition.

Propagation delay measured from the time the input signal crosses the reference (± the

input offset voltage) to the 50% point of an output high-to-low transition.

Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output low-to-high transition.

Propagation delay measured from the 50% point of the latch enable signal high-to-low

transition to the 50% point of an output high-to-low transition.

Minimum time after the negative transition of the latch enable signal that the input

signal must remain unchanged to be acquired and held at the outputs.

Minimum time that the latch enable signal must be high to acquire an input signal change.

Minimum time before the negative transition of the latch enable signal occurs that an

input signal change must be present to be acquired and held at the outputs.

Amount of time required to transition from a low-to-high output as measured at the

20% and 80% points.

Amount of time required to transition from a high-to-low output as measured at the

20% and 80% points.

Difference between the input voltages, VP and VN.

Rev. 0 | Page 5 of 16

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