AD8804 데이터 시트보기 (PDF) - Analog Devices

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AD8804

12 Channel, 8-Bit TrimDACs with Power Shutdown

Analog Devices 

AD8802/AD8804

; This 8051 µC subroutine loads an AD8802 or AD8804 DAC with an 8-bit value,

; using the 8051’s parallel port #1.

; The DAC value is stored at location DAC_VALUE

; The DAC address is stored at location DAC_ADDR

;

; Variable declarations

PORT1

DATA

90H

DAC_VALUE

DATA

40H

DAC_ADDR

DATA

41H

LOOPCOUNT

DATA

43H

;

ORG

100H

LD_8804:

ORL

PORT1,#11110000B

CLR

PORT1.5

MOV

LOOPCOUNT,#4

MOV

A,DAC_ADDR

RR

A

RR

A

RR

A

RR

A

ACALL

SEND_SERIAL

MOV

LOOPCOUNT,#8

MOV

A,DAC_VALUE

ACALL

SEND_SERIAL

SETB

PORT1.5

RET

;SFR register for port 1

;DAC Value

;DAC Address (0 through 7)

;COUNT LOOPS

;arbitrary start

;set CLK, /CS and /SHDN high

;Set Chip Select low

;Address is 4 bits

;Get DAC address

;Rotate the DAC

;address to the Most

;Significant Bits (MSBs)

;

;Send the address

;Do 8 bits of data

;Send the data

;Set /CS high

;DONE

SEND_SERIAL:

RLC

MOV

CLR

SETB

DJNZ

RET;

END

A

PORT1.7,C

PORT1.6

PORT1.6

LOOPCOUNT,SEND_SERIAL

;Move next bit to carry

;Move data to SDI

;Pulse the

;CLK input

;Loop if not done

Listing 2. Software for the 8051 to AD8802/AD8804 Parallel Port Interface

An MC68HC11-to-AD8802/AD8804 Interface

Like the 8051 µC, the MC68HC11 includes a dedicated serial

data port (labeled SPI). The SPI port provides an easy interface

to the AD8802/AD8804 (Figure 27). The interface uses three

lines of Port D for the serial data, and one or two lines from

Port C to control the SHDN and RS (AD8802 only) inputs.

MC68HC11*

(PD3) MOSI

(PD4) SCK

(PD5) SS

PC0

PC1

AD8802/

AD8804*

SDI

CLK

CS

SHDN

RS (AD8802 ONLY)

A software routine for loading the AD8802/AD8804 from a

68HC11 evaluation board is shown in Listing 3. First, the

MC68HC11 is configured for SPI operation. Bits CPHA and

CPOL define the SPI mode wherein the serial clock (SCK) is

high at the beginning and end of transmission, and data is valid

on the rising edge of SCK. This mode matches the requirements

of the AD8802/AD8804. After the registers are saved on the

stack, the DAC value and address are transferred to RAM and

the AD8802/AD8804’s CS is driven low. Next, the DAC’s ad-

dress byte is transferred to the SPDR register, which automati-

cally initiates the SPI data transfer. The program tests the SPIF

bit and loops until the data transfer is complete. Then the DAC

value is sent to the SPI. When transmission of the second byte is

complete, CS is driven high to load the new data and address

into the AD8802/AD8804.

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 26. An AD8802/AD8804-to-MC68HC11 Interface

REV. 0

–11–

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