AD8802 데이터 시트보기 (PDF) - Analog Devices
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AD8802 Datasheet PDF : 16 Pages
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AD8802/AD8804–SPECIFICATIONS (VDD = +3 V ؎ 10% or +5 V ؎ 10%, VREFH = +VDD, VREFL = 0 V, –40؇C
≤TA ≤ +85؇C unless otherwise noted)
Parameter
Symbol Conditions
Min Typ1 Max Units
STATIC ACCURACY
Specifications apply to all DACs
Resolution
Differential Nonlinearity Error
Integral Nonlinearity Error
Full-Scale Error
Zero Code Error
DAC Output Resistance
Output Resistance Match
REFERENCE INPUT
Voltage Range2
REFH Input Resistance
REFL Input Resistance3
Reference Input Capacitance3
DIGITAL INPUTS
Logic High
Logic Low
Logic High
Logic Low
Input Current
Input Capacitance3
POWER SUPPLIES4
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)
Shutdown Current
Power Dissipation
Power Supply Sensitivity
DYNAMIC PERFORMANCE3
VOUT Settling Time
Crosstalk
N
DNL
INL
GFSE
VZSE
ROUT
∆R/RO
Guaranteed Monotonic
8
Bits
–1 ± 1/4 +1
LSB
–1.5 ± 1/2 +1.5 LSB
–1 1/2
+1
LSB
–1 1/4
+1
LSB
3
5
8
kΩ
1.5
%
VREFH
VREFL
RREFH
RREFL
CREF0
CREF1
Pin Available on AD8804 Only
Digital Inputs = 55H, VREFH = VDD
Digital Inputs = 55H, VREFL = VDD
Digital Inputs all Zeros
Digital Inputs all Ones
0
VDD
V
0
VDD
V
1.2
kΩ
1.2
kΩ
32
pF
32
pF
VIH
VDD = +5 V
VIL
VDD = +5 V
VIH
VDD = +3 V
VIL
VDD = +3 V
IIL
VIN = 0 V or + 5 V
CIL
2.4
2.1
5
V
0.8
V
V
0.6
V
±1
µA
pF
VDD Range
2.7
IDD
VIH = VDD or VIL = 0 V
IDD
VIH = 2.4 V or VIL = 0.8 V, VDD = +5.5 V
IREFH
SHDN = 0
PDISS
VIH = VDD or VIL = 0 V, VDD = +5.5 V
PSRR
VDD = +5 V ± 10%
0.01
1
0.2
0.001
5.5
10
4
10
55
0.002
V
µA
mA
µA
µW
%/%
tS
± 1/2 LSB Error Band
CT
Between Adjacent Outputs5
0.6
µs
50
dB
SWITCHING CHARACTERISTICS3, 6
Input Clock Pulse Width
tCH, tCL
Clock Level High or Low
15
ns
Data Setup Time
tDS
5
ns
Data Hold Time
tDH
5
ns
CS Setup Time
tCSS
10
ns
CS High Pulse Width
tCSW
10
ns
Reset Pulse Width
tRS
90
ns
CLK Rise to CS Rise Hold Time
tCSH
20
ns
CS Rise to Clock Rise Setup
tCS1
10
ns
NOTES
1Typicals represent average readings at +25°C.
2VREFH can be any value between GND and VDD, for the AD8804 VREFL can be any value between GND and VDD.
3Guaranteed by design and not subject to production test.
4Digital Input voltages VIN = 0 V or VDD for CMOS condition. DAC outputs unloaded. PDISS is calculated from (IDD × VDD).
5Measured at a VOUT pin where an adjacent VOUT pin is making a full-scale voltage change (f = 100 kHz).
6See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V.
Specifications subject to change without notice.
–2–
REV. 0
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