AD9000 데이터 시트보기 (PDF) - Analog Devices

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AD9000

High Speed 6-Bit A/D Converter

Analog Devices 

AD9000

ABOUT THE AD9000

Analog Bandwidth

Quantifying the high frequency analog performance of the

AD9000 is somewhat difficult because of the various criteria

that can be applied. At one extreme there is the analog input

bandwidth of a single input comparator (which tends to be

extremely high). At the other end of the performance criteria is

the “no missing codes” restriction, which tends to be the most

conservative measure of analog bandwidth.

The “no missing codes” criteria simply means that the converter

is capable of generating all 64 output codes for an analog and

ENCODE frequency. At higher ENCODE rates to analog

frequencies, the converter continues to function, but with

reduced resolution. The graph below details the “no missing

codes” region of operation for the AD9000 at several reference

levels. Note that nearly all analog-to-digital converter applica-

tions operate in the oversampled region to avoid generation of

indeterminate data (aliasing).

Figure 4. Analog Input vs. Encode Rate “No Missing

Codes”

High-Speed Performance Enhancements

The AD9000 employs a hysteresis control pin which affects

comparator sensitivity. The error rate (number of full-scale

errors in a given period) is directly affected by the comparator

sensitivity. By varying the voltage on the hysteresis control pin,

the error rate can be reduced. The AD9000 is capable of ex-

tremely low error rate operation, which makes it ideal for error

sensitive applications such as QAM demodulation. If the

hysteresis control pin is used, it should be decoupled to

ground through a 0.1 µF capacitor, otherwise it may be left

floating.

At the highest encode rates, overall accuracy can be improved

by skewing the ENCODE signal duty-cycle to allow more time

in the “latch” mode. Specifically, extending the logic HIGH

portion of the ENCODE signal allows the comparators more

time to achieve an appropriate logic level prior to the decoding

cycle that begins on the rising edge of the ENCODE pulse.

Figure 5. Comparator Switching vs. Hysteresis Voltage

Layout Considerations

The AD9000, like all high-speed circuits, requires certain

precautions be taken to ensure optimum performance. The

foremost of these is the use of a substantial low impedance

ground plane around and under the AD9000. Just as important

are high quality ground connections to the AD9000 itself. It is

probably more effective to keep the analog and digital grounds

separate, except at the AD9000 where they should be connected

together. Sockets should generally be avoided due to the in-

creased interlead capacitance they induce. If socketing must be

used, pin sockets are preferred.

Decoupling is especially important to high-speed analog circuits.

Each supply should be decoupled to ground with 0.1 µF ceramic

and 0.001 µF mica capacitors. The ladder reference pins should

be treated in a similar manner. In addition to decoupling the

reference ladder, the reference ladder should be driven from a

low output impedance source for the best noise rejection. In

all cases where practical, chip capacitors are recommended to

reduce the effects of lead inductance associated with standard

discrete capacitors.

MIL-STD-883 Compliance Information

The AD9000SE/SD/883C are classified within microcircuits

group 57-technology group D (bipolar A/D converters), and are

constructed in accordance with the latest revision of MIL-STD-

883. The AD9000 is electrostatic sensitive and falls within

electrostatic sensitivity classification Category A. PDA (Percent

Defective Allowance) is computed based on Subgroups 1 of the

specified Group A test list. QA screening is in accordance with

“Alternate Method A” of method 5005. The following apply:

Burn-In per 1015, Life Test per 1005, Electrical Testing per

5004. (Note: Group A electrical Testing assumes TA = TC = TJ.)

–6–

REV. A

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