AD9142 데이터 시트보기 (PDF) - Analog Devices

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AD9142

Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter

Analog Devices 

Data Sheet

PLL Status Register .....................................................................48

IDAC FS Adjust LSB Register....................................................48

IDAC FS Adjust MSB Register ..................................................48

QDAC FS Adjust LSB Register ..................................................48

QDAC FS Adjust MSB Register ................................................49

Die Temperature Sensor Control Register...............................49

Die Temperature LSB Register ..................................................49

Die Temperature MSB Register.................................................49

Chip ID Register..........................................................................49

Interrupt Configuation Register ...............................................50

Sync CTRL Register ....................................................................50

Frame Reset CTRL Register.......................................................50

FIFO Level Configuration Register ..........................................51

FIFO Level Readback Register ..................................................51

FIFO CTRL Register...................................................................51

Data Format Select Register.......................................................52

Datapath Control Register .........................................................52

Interpolation Control Register ..................................................52

Over Threshold CTRL0 Register ..............................................53

Over Threshold CTRL1 Register ..............................................53

Over Threshold CTRL2 Register ..............................................53

Input Power Readback LSB Register ........................................53

Input Power Readback MSB Register.......................................53

NCO Control Register................................................................54

NCO_FREQ_TUNING_WORD0 Register.............................54

NCO_FREQ_TUNING_WORD1 Register.............................54

NCO_FREQ_TUNING_WORD2 Register.............................54

NCO_FREQ_TUNING_WORD3 Register.............................54

NCO_PHASE_OFFSET0 Register............................................54

REVISION HISTORY

11/12—Revision 0: Initial Version

AD9142

NCO_PHASE_OFFSET1 Register............................................55

IQ_PHASE_ADJ0 Register........................................................55

IQ_PHASE_ADJ1 Register........................................................55

IDAC_DC_OFFSET0 Register..................................................55

IDAC_DC_OFFSET1 Register..................................................55

QDAC_DC_OFFSET0 Register................................................55

QDAC_DC_OFFSET1 Register................................................56

IDAC_GAIN_ADJ Register.......................................................56

QDAC_GAIN_ADJ Register.....................................................56

Gain Step Control0 Register......................................................56

Gain Step Control1 Register......................................................56

TX Enable Control Register ......................................................57

DAC Output Control Register ..................................................57

Data Receiver Test Control Register.........................................57

Data Receiver Test Control Register.........................................57

Device Configuration0 Register................................................58

Version Register ..........................................................................58

Device Configuration1 Register................................................58

Device Configuration2 Register................................................58

DAC Latency and System Skews...................................................59

DAC Latency Variations.............................................................59

FIFO Latency Variation..............................................................59

Clock Generation Latency Variation........................................60

Correcting System Skews...........................................................60

Packaging and Ordering Information ..........................................61

Outline Dimensions....................................................................61

Ordering Guide ...........................................................................61

Rev. 0 | Page 3 of 64

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