AD9230(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD9230
(Rev.:Rev0)

12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter

Analog Devices 

TIMING DIAGRAMS

N–1

VIN

tCH

CLK+

CLK–

DCO+

DCO–

DX+

DX–

tA

N

N+1

tCL

1/fS

N+2

N+3

tCPD

tSKEW

tPD

N–7

N–6

N–5

Figure 2. Single Data Rate Mode

AD9230

N+4

N+5

N–4

N–3

VIN

CLK+

CLK–

DCO+

DCO–

D0/D6+

D0/D6–

D5/D11+

D5/D11–

N–1

tA

N

tCH

tCL

N+1

1/fS

N+2

N+3

N+4

N+5

tCPD

tSKEW

tPD

D6

N–8

D0

N–7

D6

N–7

D0

N–6

D6

N–6

D0

N–5

D6

N–5

D0

N–4

D6

N–4

D0

N–3

D11

N–8

D5

N–7

D11

N–7

D5

N–6

D11

N–6

6 MSBs

6 LSBs

Figure 3. Double Data Rate Mode

D5

N–5

D11

N–5

D5

N–4

D11

N–4

D5

N–3

Rev. 0 | Page 7 of 32

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