AD9271 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
AD9271 Datasheet PDF : 58 Pages
| |||
AD9271
Preliminary Technical Data
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 m V p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless
otherwise noted.
Table 2.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, STBY, SCLK)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D+, D−), (ANSI-644)1
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D+, D−),
(Low Power, Reduced Signal Option)1
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temperature
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Min
250
1.2
1.2
1.2
0
247
1.125
Typ
Max
Unit
CMOS/LVDS/LVPECL
1.2
20
1.5
mV p-p
V
kΩ
pF
3.6
V
0.3
V
30
kΩ
0.5
pF
3.6
V
0.3
V
70
kΩ
0.5
pF
DRVDD + 0.3 V
0.3
V
30
kΩ
2
pF
1.79
V
0.05
V
LVDS
454
mV
1.375
V
Offset binary
LVDS
Full
150
250
mV
Full
1.10
1.30
V
Offset binary
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.
Rev. PrA | Page 8 of 58
Share Link: 