AD9271 데이터 시트보기 (PDF) - Analog Devices
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AD9271 Datasheet PDF : 58 Pages
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Preliminary Technical Data
AD9271
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 m V p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless
otherwise noted.
Table 3.
Parameter1
CLOCK2
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)4
DCO to Data Delay (tDATA)4
DCO to FCO Delay (tFRAME)4
Data-to-Data Skew
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
APERTURE
Aperture Uncertainty (Jitter)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
Min
50
1.5
1.5
(tSAMPLE/24) − 300
(tSAMPLE/24) − 300
25°C
Typ
Max
10.0
10.0
2.3
300
300
2.3
tFCO +
(tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24)
±50
600
375
8
10
3.1
3.1
(tSAMPLE/24) + 300
(tSAMPLE/24) + 300
±200
<1
Unit
MSPS
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
ns
μs
CLK
cycles
ps rms
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 Can be adjusted via the SPI interface.
3 Measurements were made using a part soldered to FR4 material.
4 tSAMPLE/24 is based on the number of bits divided by 2, because the delays are based on half duty cycles.
Rev. PrA | Page 9 of 58
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