AD9279
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature, unless otherwise noted.
Table 2.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
CW 4LO INPUTS (4LO+, 4LO−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, STBY, SCLK, SDIO)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUTS (RESET)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (DOUTx+, DOUTx−), (ANSI-644)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (DOUTx+, DOUTx−),
(LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
LOGIC OUTPUT (GPO0/GPO1/GPO2/GPO3)
Logic 0 Voltage (IOL = 50 μA)
Temperature
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Min
Typ
CMOS/LVDS/LVPECL
250
1.2
20
1.5
CMOS/LVDS/LVPECL
250
1.2
20
1.5
1.2
30
0.5
1.2
30
0.5
1.2
70
0.5
1.79
247
1.125
Offset binary
LVDS
LVDS
Full
150
Full
1.10
Offset binary
Full
Max
AVDD1 + 0.3
0.3
AVDD2 + 0.3
0.3
AVDD1 + 0.3
0.3
0.05
454
1.375
250
1.30
0.05
Unit
mV p-p
V
kΩ
pF
mV p-p
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
mV
V
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.
Rev. 0 | Page 6 of 44