AD9279-65EBZ 데이터 시트보기 (PDF) - Analog Devices
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AD9279-65EBZ Datasheet PDF : 44 Pages
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AD9279
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, full temperature, unless otherwise noted.
Table 3.
Parameter1
CLOCK2
Clock Rate
40 MSPS (Mode I)
65 MSPS (Mode II)
80 MSPS (Mode III)
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)4
DCO to Data Delay (tDATA)4
DCO to FCO Delay (tFRAME)4
Data-to-Data Skew (tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby), GAIN+ = 0.5 V
Wake-Up Time (Power-Down)
Pipeline Latency
Temperature Min
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
18.5
18.5
18.5
(tSAMPLE/2) + 1.5
(tSAMPLE/2) + 1.5
(tSAMPLE/24) − 300
(tSAMPLE/24) − 300
APERTURE
Aperture Uncertainty (Jitter)
25°C
LO GENERATION
4LO Frequency
Full
4
LO Divider RESET Setup Time5
Full
5
LO Divider RESET Hold Time5
Full
5
LO Divider RESET High Pulse Width
Full
20
Typ
6.25
6.25
(tSAMPLE/2) + 2.3
300
300
(tSAMPLE/2) + 2.3
tFCO + (tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24)
±100
2
1
8
<1
Max
Unit
40
MHz
65
MHz
80
MHz
ns
ns
(tSAMPLE/2) + 3.1
(tSAMPLE/2) + 3.1
(tSAMPLE/24) + 300
(tSAMPLE/24) + 300
±350
ns
ps
ps
ns
ns
ps
ps
ps
μs
ms
Clock
cycles
ps rms
40
MHz
ns
ns
ns
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Can be adjusted via the SPI.
3 Measurements were made using a part soldered to FR-4 material.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
5 RESET edge to rising 4LO edge.
Rev. 0 | Page 7 of 44
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