AD9508(RevA) 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
AD9508 Datasheet PDF : 40 Pages
| |||
Data Sheet
Parameter
CMOS CLOCK OUTPUTS
Symbol Min
Output Frequency
Output Voltage
@ 1 mA Load
High
VOH
1.7
Low
VOL
@ 10 mA load
High
VOH
1.2
Low
VOL
@ 10 mA Load (2 × CMOS Mode)
High
VOH
1.45
Low
VOL
CMOS Duty Cycle
45
Typ Max
250
0.1
0.6
0.35
55
AD9508
Unit Test Conditions/Comments
Single-ended; termination = open; OUTx
and OUTx in phase
MHz With 10 pF load per output, see Figure 14
for swing vs. frequency
V
V
V
V
V
V
%
Up to 250 MHz
OUTPUT DRIVER TIMING CHARACTERISTICS
Table 3.
Parameter
LVDS OUTPUTS
Output Rise/Fall Time
Propagation Delay, Clock-to-LVDS Output
Temperature Coefficient
Output Skew1
All LVDS Outputs
On the Same Part
Across Multiple Parts
Symbol Min Typ
tR, tF
152
tPD
1.56 2.01
2.8
HSTL OUTPUTS
Output Rise/Fall Time
tR, tF
Propagation Delay, Clock-to-HSTL Output
tPD
Temperature Coefficient
Output Skew1
All HSTL Outputs
On the Same Part
Across Multiple Parts
118
1.59 2.05
2.9
CMOS OUTPUTS
Output Rise/Fall Time
tR, tF
Propagation Delay, Clock-to-CMOS Output tPD
Temperature Coefficient
Output Skew1
All CMOS Outputs
On the Same Part
Across Multiple Parts
1.18
2.04 2.56
3.3
Max Unit
177 ps
2.43 ns
ps/°C
Test Conditions/Comments
Termination = 100 Ω differential, 1 × LVDS
20% to 80% measured differentially
48 ps
781 ps
143 ps
2.5 ns
ps/°C
Assumes same temperature and supply;
takes into account worst-case propaga-
tion delay delta due to worst-case
process variation
Termination = 100 Ω differential, 1 × HSTL
20% to 80% measured differentially
59 ps
825 ps
Assumes same temperature and supply;
takes into account worst-case propaga-
tion delay delta due to worst-case
process variation
1.45 ns
3.07 ns
ps/°C
20% to 80%; CLOAD = 10 pF
10 pF load
112 ps
965 ps
Assumes same temperature and supply;
takes into account worst-case
propagation delay delta due to worst-
case process variation
Rev. A | Page 5 of 40
Share Link: 