AD9511 데이터 시트보기 (PDF) - Analog Devices
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AD9511 Datasheet PDF : 60 Pages
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AD9511
Parameter
NOISE CHARACTERISTICS
In-Band Noise of the Charge Pump/
Phase Frequency Detector (In-Band
Means Within the LBW of the PLL)
@ 50 kHz PFD Frequency
@ 2 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
PLL Figure of Merit
PLL DIGITAL LOCK DETECT WINDOW4
Required to Lock
(Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns Only)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
To Unlock After Lock (Hysteresis)4
Low Range (ABP 1.3 ns, 2.9 ns Only)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
Min Typ
Max Unit Test Conditions/Comments
−172
−156
−149
−142
−218 +
10 × log (fPFD)
3.5
7.5
3.5
7
15
11
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
The synthesizer phase noise floor is
estimated by measuring the in-band
phase noise at the output of the VCO and
subtracting 20logN (where N is the
N divider value).
Approximation of the PFD/CP phase noise
floor (in the flat region) inside the PLL loop
bandwidth. When running closed loop this
phase noise is gained up by 20 × log(N)3.
Signal available at STATUS pin
when selected by 08h<5:2>.
Selected by Register ODh.
ns
<5> = 1b.
ns
<5> = 0b.
ns
<5> = 0b.
Selected by Register 0Dh.
ns
<5> = 1b.
ns
<5> = 0b.
ns
<5> = 0b.
1 REFIN and REFINB self-bias points are offset slightly to avoid chatter on an open input condition.
2 CLK2 is electrically identical to CLK1; the distribution only input can be used as differential or single-ended input (see the Clock Inputs section).
3 Example: −218 + 10 × log(fPFD) + 20 × log(N) should give the values for the in-band noise at the VCO output.
4 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
CLOCK INPUTS
Table 2.
Parameter
CLOCK INPUTS (CLK1, CLK2)1
Input Frequency
Input Sensitivity
Input Level
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Min Typ Max Unit
Test Conditions/Comments
0
1.6 GHz
1502
mV p-p Jitter performance can be improved with higher slew
rates (greater swing).
23
V p-p
Larger swings turn on the protection diodes and can
degrade jitter performance.
1.5 1.6 1.7 V
Self-biased; enables ac coupling.
1.3
1.8 V
With 200 mV p-p signal applied; dc-coupled.
150
mV p-p CLK2 ac-coupled; CLK2B ac bypassed to RF ground.
4.0 4.8 5.6 kΩ
Self-biased.
2
pF
1 CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input.
2 With a 50 Ω termination, this is −12.5 dBm.
3 With a 50 Ω termination, this is +10 dBm.
Rev. A | Page 5 of 60
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