AD9511 데이터 시트보기 (PDF) - Analog Devices

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AD9511

1.2Ghz Clock Distribution IC / PLL Core / Divider / Delay Adjust / 8 Outputs

Analog Devices 

TIMING CHARACTERISTICS

Table 4.

Parameter

LVPECL

Output Rise Time, tRP

Output Fall Time, tFP

PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT1

Divide = Bypass

Divide = 2 − 32

Variation with Temperature

OUTPUT SKEW, LVPECL OUTPUTS

OUT1 to OUT0 on Same Part, tSKP2

OUT1 to OUT2 on Same Part, tSKP2

OUT0 to OUT2 on Same Part, tSKP2

All LVPECL OUT Across Multiple Parts, tSKP_AB3

Same LVPECL OUT Across Multiple Parts, tSKP_AB3

LVDS

Output Rise Time, tRL

Output Fall Time, tFL

PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT1

OUT3 to OUT4

Divide = Bypass

Divide = 2 − 32

Variation with Temperature

OUTPUT SKEW, LVDS OUTPUTS

OUT3 to OUT4 on Same Part, tSKV2

All LVDS OUTs Across Multiple Parts, tSKV_AB3

Same LVDS OUT Across Multiple Parts, tSKV_AB3

CMOS

Output Rise Time, tRC

Output Fall Time, tFC

PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT1

Divide = Bypass

Divide = 2 − 32

Variation with Temperature

OUTPUT SKEW, CMOS OUTPUTS

OUT3 to OUT4 on Same Part, tSKC2

All CMOS OUT Across Multiple Parts, tSKC_AB3

Same CMOS OUT Across Multiple Parts, tSKC_AB3

LVPECL-TO-LVDS OUT

Output Skew, tSKP_V

LVPECL-TO-CMOS OUT

Output Skew, tSKP_C

LVDS-TO-CMOS OUT

Output Skew, tSKV_C

AD9511

Min Typ

130

130

Max Unit Test Conditions/Comments

Termination = 50 Ω to VS − 2 V

Output level 3Dh (3Eh) (3Fh)<3:2> = 10b

180 ps

20% to 80%, measured differentially

180 ps

80% to 20%, measured differentially

335 490

375 545

0.5

635 ps

695 ps

ps/°C

70 100 140 ps

15 45

80 ps

45 65

90 Ps

275 ps

130 ps

Termination = 100 Ω differential

Output level 40h (41h) <2:1> = 01b

3.5 mA termination current

200 350 ps

20% to 80%, measured differentially

210 350 ps

80% to 20%, measured differentially

Delay off on OUT4

0.99 1.33

1.04 1.38

0.9

−85

681

646

1.02 1.39

1.07 1.44

1

−140 +145

0.74 0.92

0.88 1.14

158 353

1.59

1.64

+270

450

325

865

992

1.71

1.76

+300

650

500

1.14

1.43

506

ns

ns

ps/°C

ps

ps

ps

ps

ps

ns

ns

ps/°C

ps

ps

ns

ns

ps

Delay off on OUT4

B outputs are inverted; termination = open

20% to 80%; CLOAD = 3 pF

80% to 20%; CLOAD = 3 pF

Delay off on OUT4

Delay off on OUT4

Everything the same; different logic type

LVPECL to LVDS on same part

Everything the same; different logic type

LVPECL to CMOS on same part

Everything the same; different logic type

LVDS to CMOS on same part

Rev. A | Page 7 of 60

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