AD9513 데이터 시트보기 (PDF) - Analog Devices

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AD9513

800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

Analog Devices 

AD9513

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Clock Input.................................................................................... 3

Clock Outputs ............................................................................... 3

Timing Characteristics ................................................................ 4

Clock Output Phase Noise .......................................................... 6

Clock Output Additive Time Jitter............................................. 8

SYNCB, VREF, and Setup Pins ................................................... 9

Power.............................................................................................. 9

Timing Diagrams............................................................................ 10

Absolute Maximum Ratings.......................................................... 11

Thermal Characteristics1 ........................................................... 11

Pin Configuration and Function Descriptions........................... 12

Terminology .................................................................................... 13

Typical Performance Characteristics ........................................... 14

Functional Description .................................................................. 17

Overall.......................................................................................... 17

CLK, CLKB—Differential Clock Input ................................... 17

Synchronization .......................................................................... 17

REVISION HISTORY

10/2017—Rev. A to Rev. B

Changed CP-32-7 to CP-32-2 ...................................... Throughout

Updated Outline Dimensions ....................................................... 26

Changes to Ordering Guide .......................................................... 26

1/2017—Rev. 0 to Rev. A

Changes to Figure 5 and Table 9................................................... 12

Deleted Figure 6; Renumbered Sequentially............................... 12

Change to Table 14 ......................................................................... 19

Updated Outline Dimensions ....................................................... 26

Changes to Ordering Guide .......................................................... 26

9/2005—Revision 0: Initial Version

Data Sheet

Power-On SYNC .................................................................... 17

SYNCB..................................................................................... 17

RSET Resistor ............................................................................. 18

VREF ............................................................................................ 18

Setup Configuration................................................................... 18

Divider Phase Offset .................................................................. 20

Delay Block ................................................................................. 21

Outputs ........................................................................................ 21

Power Supply............................................................................... 22

Exposed Metal Paddle ........................................................... 22

Power Management.................................................................... 22

Applications Information .............................................................. 23

Using the AD9513 Outputs for ADC Clock Applications .... 23

LVDS Clock Distribution .......................................................... 23

CMOS Clock Distribution ........................................................ 23

Setup Pins (S0 to S10) ................................................................ 24

Power and Grounding Considerations and Power Supply

Rejection ...................................................................................... 24

Phase Noise and Jitter Measurement Setups........................... 25

Outline Dimensions ....................................................................... 26

Ordering Guide .......................................................................... 26

Rev. B | Page 2 of 28

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