AD9525(Rev0) 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

제조사

AD9525
(Rev.:Rev0)

Low Jitter Clock Generator with Eight LVPECL Outputs

Analog Devices 

AD9525

Parameter

CLK = 1474.56 MHz, FOUT = 1474.56 MHz

Divider = 1

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 800 kHz Offset

At 1 MHz Offset

At 10 MHz Offset

CLK = 122.88 MHz, FOUT = 122.88 MHz

Divider = 1

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 800 kHz Offset

At 1 MHz Offset

At 10 MHz Offset

PD, RESET, AND REF_SEL PINS

Table 17.

Parameter

INPUT CHARACTERISTICS

Logic 1 Voltage

Logic 0 Voltage

Logic 1 Current

Logic 0 Current PD, RESET

Logic 0 Current REF_SEL

Capacitance

RESET TIMING

Pulse Width Low

RESET Inactive to Start of Register

Programming

STATUS AND REF_MON PINS

Table 18.

Parameter

OUTPUT CHARACTERISTICS

Output Voltage High, VOH

Output Voltage Low, VOL

MAXIMUM TOGGLE RATE

Min Typ

Max Unit

Test Conditions/Comments

Data Sheet

−114

−125

−134

−144

−149

−151

−151

−154

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

−134

−145

−153

−159

−161

−161

−161

−161

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

Min Typ Max Unit

2.0

V

0.8 V

1

µA

−112

µA

1

µA

2

pF

50

ns

100

ns

Test Conditions/Comments

The minus sign indicates that current is flowing out of

the AD9525, which is due to the internal pull-up

resistor

Min Typ Max Unit

2.7

V

0.4 V

200

MHz

Test Conditions/Comments

1 mA output load

Applies when mux is set to any divider or counter

output or PFD up/down pulse; usually debug mode

only; beware that spurs can couple to output when any

of these pins is toggling

Rev. 0 | Page 10 of 48

Share Link: