AD9525(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD9525
(Rev.:Rev0)

Low Jitter Clock Generator with Eight LVPECL Outputs

Analog Devices 

Data Sheet

AD9525

CLOCK INPUTS

Table 6.

Parameter

Input Frequency

Input Sensitivity

Input Level

Input Common-Mode Voltage, VCM

Input Common-Mode Range, VCMR

Input Resistance

Input Capacitance

Min Typ Max Unit Test Conditions/Comments

0

3.6 GHz Frequencies below ~1 MHz should be dc-coupled; be careful to

match self-bias voltage

150

mV p-p Measured at 3.1 GHz

2

V p-p Larger voltage swings can turn on the protection diodes and

can degrade jitter performance

1.55 1.64 1.74 V

Self-biased; enables ac coupling

1.3

1.8 V

With 200 mV p-p signal applied; dc-coupled

6.7 7

7.4 kΩ

Self-biased

2

pF

PLL CHARACTERISTICS

Table 7.

Parameter

Min Typ Max Unit Test Conditions/Comments

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency

125 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns

45 MHz Antibacklash pulse width = 6.0 ns

CHARGE PUMP (CP)

VDD_CP (Pin 13); VCP is the voltage of the charge pump pin

(CP, Pin 14)

ICP Sink/Source

Programmable

High Value

4.5 4.9 5.4 mA

With CPRSET = 5.1 kΩ; higher ICP is possible by changing

CPRSET; VCP = VDD_CP/2 V

Low Value

0.57 0.61 0.67 mA

With CPRSET = 5.1 kΩ; lower ICP is possible by changing

CPRSET, VCP = VDD_CP/2 V

Absolute Accuracy

2.5

%

VCP = VDD_CP/2 V

CPRSET Range

2.7

10 kΩ

ICP High Impedance Mode Leakage

3.5

µA

VDD_CP = 5 V

Sink-and-Source Current Matching

2

%

0.5 V < VCP < VDD_CP − 0.5 V

ICP vs. VCP

1.5

%

0.5 V < VCP < VDD_CP − 0.5 V

ICP vs. Temperature

2

%

VCP = VDD_CP/2 V

P DIVIDER (PART OF N DIVIDER)

Input Frequency P = 1

1500 MHz

Input Frequency P = 2

3000 MHz

Input Frequency P = 3

3600 MHz

Input Frequency P = 4

3600 MHz

Input Frequency P = 5

3600 MHz

Input Frequency P = 6

3600 MHz

B DIVIDER (PART OF N DIVIDER)

Input Frequency

1500 MHz

B counter input frequency (N Divider input frequency

divided by P)

M DIVIDER

Input Frequency

3600 MHz

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge Pump/

Phase Frequency Detector (In-Band

Means Within the LBW of the PLL)

PLL in-band phase noise floor is estimated by measuring the

in-band phase noise at the output of the VCO and subtracting

20 log(N) (where N is the value of the N divider)

At 61.44 MHz PFD Frequency

−144

dBc/Hz

At 122.88 MHz PFD Frequency

−141

dBc/Hz

PLL Figure of Merit (FOM)

−222

dBc/Hz

Reference slew rate > 0.25 V/ns; FOM +10 log (fPFD) is an

approximation of the PFD/CP in-band phase noise (in the

flat region) inside the PLL loop bandwidth; when running

closed loop, the phase noise, as observed at the VCO output,

is increased by 20 log(N)

Rev. 0 | Page 5 of 48

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