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AD9525

Low Jitter Clock Generator with Eight LVPECL Outputs

Analog Devices 

Data Sheet

Reference Switchover

The AD9525 supports two separate differential reference inputs.

Manual switchover is performed between these inputs either

through Register 0x01A or by using the REF_SEL pin. This

feature supports networking and other applications that require

redundant references.

Manual switchover requires that a clock be present on the reference

input that is being switched to or that the switchover deglitching

feature be disabled (Register 0x01A[4]).

Reference Dividers R

The reference inputs are routed to their respective divider, R. R can

be set to any value from 1 to 32 (Both R = 0 and R = 1 give divide-

by-1.).

The division is set by the values of RLOW and RHIGH. The divider

can be bypassed (equivalent to divide-by-1, divider circuit is

powered down) by setting the bypass bit.

For each R divider, the frequency division (RX) is set by the values

of RLOW and RHIGH (four bits each, representing Decimal 0 to

Decimal 15), where

Number of Low Cycles = RLOW + 1

Number of High Cycles = RHIGH + 1

The high and low cycles are cycles of the clock signal currently

routed to the input of the R.

When a divider is bypassed, RX = 1.

Otherwise, RX = (RHIGH + 1) + (RLOW + 1) = RHIGH + RLOW + 2.

This allows each reference divider to divide by any integer from

1 to 32.

The output of the R divider goes to a mux to select one of the

references to the PFD inputs. The frequency applied to the PFD

must not exceed the maximum allowable frequency, which

depends on the antibacklash pulse setting (see Table 7).

The R divider has its own reset. The R divider can also be reset

using the shared reset bit of the R and B counters. This reset bit

is not self-clearing.

The R divider in the REFC path has a division ratio programmable

from 1 to 127.

VCO/VCXO, M and N Feedback Dividers

The feedback division is the product of the M divider and the

N divider. The N divider is a combination of a prescaler (P) and

a B divider.

fVCO = (fREF/R) × N × M

where:

M =1, 2, 3, 4, 5, or 6.

N = (P × B).

P =1, 2, 3, 4, 5, or 6.

B = 1, 2, 3, … or 32.

AD9525

M Divider

The M divider is a fixed divide (FD) of 1, 2, 3, 4, 5, or 6.

The maximum input frequency to the M counter is reflected in

the maximum CLKIN input frequency specified in Table 6.

The M divider provides frequency division between the CLKIN

input and the N feedback divider and clock distribution output

channels.

The M divider can also be set to static, which is useful for

applications where the only desired output frequency is the

CLK input frequency.

P Divider

The P divider is a fixed divide (FD) of 1, 2, 3, 4, 5 or 6.

The maximum input frequency to the P counter is reflected in

the maximum CLKIN input frequency specified in Table 6.

B Divider

The B divider is a fixed divide (FD) of 1, 2, 3, …or 32.

The maximum input frequency to the B counter is ~1500 MHz,

as specified in Table 7. This is the prescaler input frequency

(external VCO or CLKIN) divided by the P and M counters.

For example, M = 1 and P = 1 mode is not allowed if the

external VCO frequency is greater than 1500 MHz because the

frequency going to the B divider is too high.

The division is set by the values of BLOW and BHIGH. The divider

can be bypassed (equivalent to divide-by-1, divider circuit is

powered down) by setting the bypass bit.

The frequency division, BX, is set by the values of BLOW and

BHIGH (four bits each, representing Decimal 0 to Decimal 15),

where

Number of Low Cycles = BLOW + 1

Number of High Cycles = BHIGH + 1

The high and low cycles are cycles of the clock signal currently

routed to the input of the B divider.

When a divider is bypassed, BX = 1.

Otherwise, BX = (BHIGH + 1) + (BLOW + 1) = BHIGH + BLOW + 2.

Although manual reset is not normally required, the B counter has

its own reset bit. Note that this reset bit is not self-clearing.

Rev. A | Page 21 of 48

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