AD9525 데이터 시트보기 (PDF) - Analog Devices

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AD9525

Low Jitter Clock Generator with Eight LVPECL Outputs

Analog Devices 

Data Sheet

AD9525

CONTROL REGISTERS

CONTROL REGISTER MAP OVERVIEW

Register addresses that are not listed in Table 28 are not used,

and writing to those registers has no effect. Registers that are

marked as reserved should never have their values changed.

When writing to registers with bits that are marked reserved,

the user should take care to always write the default value for

the reserved bits.

Table 28. Control Register Map

Reg.

Addr.

(Hex)

Register

Name

(MSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Bit 0

Serial Port Configuration

0x000

SPI mode

serial port

configuration

SD0

active

LSB first/

address

increase

Soft reset

Don't care Don't care

Soft

reset

LSB first/

address

increase

SD0 active

Don't

care

Don't care

Soft reset

Don't care Don't care

Soft

reset

Don't care

Don't care

0x004 Readback

control

Don't

care

Don't care

Don't care

Don't care Don't care

Don't

care

Don't care

Read back

active regs

PLL Configuration

0x010 PFD charge

pump

PFD

polarity

CP current, Bits[2:0]

CP mode, Bits[1:0]

Antibacklash pulse width,

Bits[1:0]

0x011 R dividers

REFB divider output high cycles, Bits[3:0]

REFB divider output low cycles, Bits[3:0]

0x012

REFA divider output high cycles, Bits[3:0]

REFA divider output low cycles, Bits[3:0]

0x013 B divider

B divider output high cycles, Bits[3:0]

B divider output low cycles, Bits[3:0]

0x014 N divider

Don't

care

Don't care

B divider bypass

REFB

divider

bypass

REFA divider

bypass

P divider prescaler, Bits[2:0]

0x015 Resets

Don't

care

Reserved

Reserved

Reserved

B divider reset

REFB

divider

reset

REFA

divider reset

Reset all

dividers

0x016 REFC

REFC

enable

REFC divider, Bits[6:0]

0x017 Status pin

Charge

pump

pin to

VDD_CP/2

STATUS pin

divider enable

STATUS output select, Bits[5:0]

0x018 REF_MON pin Don’t

control

care

Don’t care

Don’t care

REF_MON pin control, Bits[4:0]

0x019 Lock detect

Don't

care

Don't care

Don't care

Don’t care Lock detect counter, Bits[1:0] Digital lock

Digital lock

detect window det disable

0x01A

Ref

switchover

and monitors

Enable

FB clock

present

monitor

Enable REFA

present

monitor

Enable REFB

present monitor

Disable

switchover

deglitch

Select REFB

(manual

register

mode)

Stay on

REFB

Use REF_SEL

pin for

reference

switchover

Enable

automatic

reference

switchover

0x01B Reserved

0x01C PLL block PD

register

0x01F PLL readback

Reserved

=0

N divider

ECL 2

CMOS PD

Unused

Reserved = 0

N divider PD

Unused

PECL/CMOS Outputs

0x0F0 LVPECL OUT0

Don’t

care

Don’t care

0x0F1 LVPECL OUT1

0x0F2 LVPECL OUT2

Don’t

care

Don’t

care

Don’t care

Don’t care

0x0F3 LVPECL OUT3 Don’t

care

Don’t care

Reserved = 0

R Divider B ECL 2

CMOS PD

Unused

Reserved =

0

R Divider A

ECL 2

CMOS PD

Selected

reference

Reserved = 0

R Divider B PD

Status FB clock

R

Divider A

PD

Status

REFB

Reserved = 0

R Channel B

PD

Status REFA

Don’t care

Don’t care

Don’t care

Don’t care

Power

down

Channel 0,

Channel 1

Reserved

Don't care

Don't care

Power

down

Channel 2,

Channel 3

Reserved

Don't care

Don't care

OUT0 PECL output level,

Bits[1:0]

OUT1 PECL output level,

Bits[1:0]

OUT2 PECL output level,

Bits[1:0]

OUT3 PECL output level,

Bits[1:0]

Reserved = 0

R Channel A

PD

Digital lock

detect (DLD)

Power down

PECL driver

Power down

PECL driver

Power down

PECL driver

Power down

PECL driver

Default

Value

(Hex)

0x00

0x00

0x00

0x7D

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x22

N/A

0x04

0x04

0x04

0x04

Rev. A | Page 31 of 48

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