AD9540 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

제조사

AD9540

655 MHz Low Jitter Clock Generator

Analog Devices 

AD9540

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Overview............................................................................. 3

Specifications..................................................................................... 4

Loop Measurement Conditions.................................................. 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Typical Application Circuits.......................................................... 17

Application Circuit Descriptions ............................................. 18

Theory of Operation ...................................................................... 19

PLL Circuitry .............................................................................. 19

REVISION HISTORY

2/06—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

Changes to Applications Section .................................................... 1

Changes to Functional Block Diagram.......................................... 1

Changes to Table 1............................................................................ 4

Changes to Typical Application Circuits Section....................... 17

Updates to Ordering Guide........................................................... 32

7/04—Revision 0: Initial Version

CML Driver................................................................................. 19

DDS and DAC ............................................................................ 20

Modes of Operation ....................................................................... 21

Selectable Clock Frequencies and Selectable Edge Delay ..... 21

Synchronization Modes for Multiple Devices.............................. 21

Serial Port Operation ..................................................................... 22

Instruction Byte .......................................................................... 23

Serial Interface Port Pin Description....................................... 23

MSB/LSB Transfers .................................................................... 23

Register Map and Description ...................................................... 24

Control Register Bit Descriptions ............................................ 27

Outline Dimensions ....................................................................... 32

Ordering Guide .......................................................................... 32

Rev. A | Page 2 of 32

Share Link: