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AD9520-5

12 LVPECL/24 CMOS Output Clock Generator

Analog Devices

AD9520-5 Datasheet PDF : 74 Pages

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AD9520-5

Data Sheet

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

Table 6.

Parameter

CLK-TO-LVPECL ADDITIVE PHASE NOISE

CLK = 1 GHz, Output = 1 GHz

Divider = 1

10 Hz Offset

100 Hz Offset

1 kHz Offset

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

100 MHz Offset

CLK = 1 GHz, Output = 200 MHz

Divider = 5

10 Hz Offset

100 Hz Offset

1 kHz Offset

10 kHz Offset

100 kHz Offset

1 MHz Offset

>10 MHz Offset

CLK-TO-CMOS ADDITIVE PHASE NOISE

CLK = 1 GHz, Output = 250 MHz

Divider = 4

10 Hz Offset

100 Hz Offset

1 kHz Offset

10 kHz Offset

100 kHz Offset

1 MHz Offset

>10 MHz Offset

CLK = 1 GHz, Output = 50 MHz

Divider = 20

10 Hz Offset

100 Hz Offset

1 kHz Offset

10 kHz Offset

100 kHz Offset

1 MHz Offset

>10 MHz Offset

Min Typ Max Unit

Test Conditions/Comments

Distribution section only; does not include the PLL

Input slew rate > 1 V/ns

−107

−117

−127

−135

−142

−145

−147

−150

dBc/Hz

Input slew rate > 1 V/ns

−122

−132

−143

−150

−156

−157

dBc/Hz

Distribution section only; does not include the PLL

Input slew rate > 1 V/ns

−107

−119

−125

−134

−144

−148

−154

dBc/Hz

Input slew rate > 1 V/ns

−126

−133

−140

−148

−157

−160

−163

dBc/Hz

Rev. B | Page 10 of 74

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