AD9520-5 데이터 시트보기 (PDF) - Analog Devices

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AD9520-5

12 LVPECL/24 CMOS Output Clock Generator

Analog Devices 

Data Sheet

AD9520-5

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

Table 7.

Parameter

LVPECL OUTPUT ABSOLUTE TIME JITTER

LVPECL = 245.76 MHz; PLL LBW = 125 Hz

LVPECL = 122.88 MHz; PLL LBW = 125 Hz

LVPECL = 61.44 MHz; PLL LBW = 125 Hz

Min Typ Max Unit

54

fs rms

77

fs rms

109

fs rms

79

fs rms

114

fs rms

163

fs rms

124

fs rms

176

fs rms

259

fs rms

Test Conditions/Comments

Application example based on a typical setup using an

external 245.76 MHz VCXO (Toyocom TCO-2112);

reference = 15.36 MHz; R DIV = 1

Integration BW = 200 kHz to 5 MHz

Integration BW = 200 kHz to 10 MHz

Integration BW = 12 kHz to 20 MHz

Integration BW = 200 kHz to 5 MHz

Integration BW = 200 kHz to 10 MHz

Integration BW = 12 kHz to 20 MHz

Integration BW = 200 kHz to 5 MHz

Integration BW = 200 kHz to 10 MHz

Integration BW = 12 kHz to 20 MHz

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

Table 8.

Parameter

LVPECL OUTPUT ADDITIVE TIME JITTER

CLK = 622.08 MHz

Any LVPECL Output = 622.08 MHz

Divide Ratio = 1

CLK = 622.08 MHz

Any LVPECL Output = 155.52 MHz

Divide Ratio = 4

CLK = 1000 MHz

Any LVPECL Output = 100 MHz

Divide Ratio = 10

CLK = 500 MHz

Any LVPECL Output = 100 MHz

Divide Ratio = 5

CMOS OUTPUT ADDITIVE TIME JITTER

CLK = 200 MHz

Any CMOS Output Pair = 100 MHz

Divide Ratio = 2

Min Typ Max Unit Test Conditions/Comments

Distribution section only; does not include the PLL;

measured at rising edge of the clock signal

46

fs rms Integration bandwidth = 12 kHz to 20 MHz

64

fs rms Integration bandwidth = 12 kHz to 20 MHz

223

fs rms Calculated from SNR of ADC method

Broadband jitter

209

fs rms Calculated from SNR of ADC method

Broadband jitter

Distribution section only; does not include the PLL

325

fs rms Calculated from SNR of ADC method

Broadband jitter

Rev. B | Page 11 of 74

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