AD9520-5BCPZ-REEL7 데이터 시트보기 (PDF) - Analog Devices
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AD9520-5BCPZ-REEL7 Datasheet PDF : 74 Pages
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Data Sheet
AD9520-5
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
Input Frequency
Min Typ Max Unit
01
2.4
GHz
01
2.0
GHz
Input Sensitivity, Differential
01
1.6
GHz
150
mV p-p
Input Level, Differential
2
V p-p
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
1.3
1.57 1.8
V
1.3
1.8
V
150
mV p-p
3.9
4.7 5.7
kΩ
2
pF
1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5,
OUT6, OUT7, OUT8, OUT9, OUT10,
OUT11
Output Frequency, Maximum
Min Typ Max Unit
2400
MHz
Output High Voltage, VOH
Output Low Voltage, VOL
Output Differential Voltage, VOD
VS_DRV − VS_DRV VS_DRV
V
1.07 − 0.96 − 0.84
VS_DRV − VS_DRV VS_DRV
V
1.95 − 1.79 − 1.64
660
820 950
mV
CMOS CLOCK OUTPUTS
OUT0A, OUT0B, OUT1A, OUT1B, OUT2A,
OUT2B, OUT3A, OUT3B, OUT4A, OUT4B,
OUT5A, OUT5B, OUT6A, OUT6B, OUT7A,
OUT7B, OUT8A, OUT8B, OUT9A, OUT9B,
OUT10A, OUT10B, OUT11A, OUT11B
Output Frequency
Output Voltage High, VOH
VS −
0.1
Output Voltage Low, VOL
Output Voltage High, VOH
2.7
Output Voltage Low, VOL
Output Voltage High, VOH
1.8
Output Voltage Low, VOL
250
MHz
V
0.1
V
V
0.5
V
V
0.6
V
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed); this is the
frequency range supported by the channel divider for all
divide ratios except divide-by-17 and divide-by-3
Distribution only (VCO divider bypassed); this is the
frequency range supported by all channel divider ratios
Measured at 2.4 GHz; jitter performance is improved with
slew rates > 1 V/ns ; the input sensitivity is sufficient for
ac-coupled LVDS and LVPECL signals
Larger voltage swings can turn on the protection diodes
and can degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Test Conditions/Comments
Termination = 50 Ω to VS_DRV − 2 V
Differential (OUT, OUT)
Using direct to output (see Figure 17); higher frequencies
are possible, but the resulting amplitude does not meet the
VOD specification; the maximum output frequency is limited
by the maximum frequency at the CLK inputs
VOH − VOL for each leg of a differential pair for default
amplitude setting with the driver not toggling; the peak-to-
peak amplitude measured using a differential probe across
the differential pair with the driver toggling is roughly 2×
these values (see Figure 17 for variation over frequency)
Single-ended; termination = 10 pF
See Figure 18
1 mA load, VS_DRV = 3.3 V/2.5 V
1 mA load, VS_DRV = 3.3 V/2.5 V
10 mA load, VS_DRV = 3.3 V
10 mA load, VS_DRV = 3.3 V
10 mA load, VS_DRV = 2.5 V
10 mA load, VS_DRV = 2.5 V
Rev. B | Page 7 of 74
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