AD9520-5BCPZ-REEL7 데이터 시트보기 (PDF) - Analog Devices
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AD9520-5BCPZ-REEL7 Datasheet PDF : 74 Pages
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AD9520-5
Parameter
Source Current
Static
Dynamic
Sink Current
Static
Dynamic
Min Typ Max Unit
20
mA
16
mA
8
mA
16
mA
Data Sheet
Test Conditions/Comments
Damage to the part can result if values are exceeded
Damage to the part can result if values are exceeded
TIMING CHARACTERISTICS
Table 5.
Parameter
Min
LVPECL OUTPUT RISE/FALL TIMES
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL
OUTPUT
For All Divide Values
850
800
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS1
LVPECL Outputs Sharing the Same Divider
LVPECL Outputs on Different Dividers
All LVPECL Outputs Across Multiple Parts
CMOS OUTPUT RISE/FALL TIMES
Output Rise Time, tRC
Output Fall Time, tFC
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS
OUTPUT
For All Divide Values
2.1
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS1
CMOS Outputs Sharing the Same Divider
All CMOS Outputs on Different Dividers
All CMOS Outputs Across Multiple Parts
OUTPUT SKEW, LVPECL-TO-CMOS OUTPUTS1
Outputs Sharing the Same Divider
1.18
Outputs on Different Dividers
1.20
Typ Max Unit
130 170
ps
130 170
ps
1050
970
1.0
1280
1180
ps
ps
ps/°C
5
16
ps
5
20
ps
5
45
ps
5
60
ps
190
ps
750 960
ps
715 890
ps
965 1280 ps
890 1100 ps
2.75 3.55
3.35
2
7
85
10
105
10
240
10
285
600
620
1.76 2.48
1.78 2.50
ns
ns
ps/°C
ps
ps
ps
ps
ps
ps
ns
ns
Test Conditions/Comments
Termination = 50 Ω to VS_DRV − 2 V
20% to 80%, measured differentially (rise/fall times are
independent of VS and are valid for VS_DRV = 3.3 V and 2.5 V)
80% to 20%, measured differentially (rise/fall times are
independent of VS and are valid for VS_DRV = 3.3 V and 2.5 V)
High frequency clock distribution configuration
Clock distribution configuration
Termination = 50 Ω to VS_DRV − 2 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V and 2.5 V
Termination = open
20% to 80%; CLOAD = 10 pF; VS_DRV = 3.3 V
80% to 20%; CLOAD = 10 pF; VS_DRV = 3.3 V
20% to 80%; CLOAD = 10 pF; VS_DRV = 2.5 V
80% to 20%; CLOAD = 10 pF; VS_DRV = 2.5 V
Clock distribution configuration
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V and 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
All settings identical; different logic type
LVPECL to CMOS on same part
LVPECL to CMOS on same part
1 The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
Rev. B | Page 8 of 74
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