AD9520-5BCPZ 데이터 시트보기 (PDF) - Analog Devices

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AD9520-5BCPZ

12 LVPECL/24 CMOS Output Clock Generator

Analog Devices 

Data Sheet

Timing Diagrams

DIFFERENTIAL

80%

20%

LVPECL

tRP

tFP

Figure 2. LVPECL Timing, Differential

CLK

tCLK

tPECL

tCMOS

Figure 3. CLK/CLK to Clock Output Timing, DIV = 1

AD9520-5

SINGLE-ENDED

80%

20%

CMOS

10pF LOAD

tRC

tFC

Figure 4. CMOS Timing, Single-Ended, 10 pF Load

Rev. B | Page 9 of 74

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