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AD9751 데이터 시트보기 (PDF) - Analog Devices

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AD9751 Datasheet PDF : 28 Pages
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AD9751
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
RESET 1
CLK+ 2
CLK– 3
DCOM 4
DVDD 5
PLLLOCK 6
MSB–P1B9 7
P1B8 8
P1B7 9
P1B6 10
P1B5 11
P1B4 12
PIN 1
IDENTIFIER
AD9751
TOP VIEW
(Not to Scale)
36 RESERVED
35 RESERVED
34 RESERVED
33 RESERVED
32 P2B0–LSB
31 P2B1
30 P2B2
29 P2B3
28 P2B4
27 P2B5
26 P2B6
25 P2B7
13 14 15 16 17 18 19 20 21 22 23 24
RESERVED = NO
USER CONNECTIONS
Pin No.
1
2
3
4, 22
5, 21
6
7–16
17–20, 33–36
23–32
37, 38
39
40
41
42
43
44
45
46
47
48
Mnemonic
RESET
CLK+
CLK–
DCOM
DVDD
PLLLOCK
P1B9–P1B0
RESERVED
P2B9–P2B0
DIV0, DIV1
REFIO
FSADJ
AVDD
IOUTB
IOUTA
ACOM
CLKCOM
LPF
PLLVDD
CLKVDD
PIN FUNCTION DESCRIPTIONS
Description
Internal Clock Divider Reset
Differential Clock Input
Differential Clock Input
Digital Common
Digital Supply Voltage
Phase-Locked Loop Lock Indicator Output
Data Bits P1B9 to P1B0, Port 1
Data Bits P2B9 to P2B0, Port 2
Control Inputs for PLL and Input Port Selector Mode; see Tables I and II for details.
Reference Input/Output
Full-Scale Current Output Adjust
Analog Supply Voltage
Differential DAC Current Output
Differential DAC Current Output
Analog Common
Clock and Phase-Locked Loop Common
Phase-Locked Loop Filter
Phase-Locked Loop Supply Voltage
Clock Supply Voltage
–6–
REV. C

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