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AD9764(Rev_B) 데이터 시트보기 (PDF) - Analog Devices

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AD9764
(Rev.:Rev_B)
ADI
Analog Devices ADI
AD9764 Datasheet PDF : 22 Pages
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AD9764
AVDD
AVDD
1.2V
AD1580
OPTIONAL
BANDLIMITING
CAPACITOR
REFLO
COMP1 AVDD
RFB
VDD
OUT1
AD7524 VREF
OUT2
AGND
DB7–DB0
0.1V TO 1.2V
RSET
IREF =
VREF/RSET
+1.2V REF
REFIO
FS ADJ
AD9764
50pF
CURRENT
SOURCE
ARRAY
Figure 25. Single-Supply Gain Control Circuit
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed, and IREF is
varied by an external voltage, VGC, applied to RSET via an ampli-
fier. An example of this method is shown in Figure 26 in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, VGC, is
referenced to ACOM and should not exceed 1.2 V. The value of
RSET is such that IREFMAX and IREFMIN do not exceed 62.5 µA
and 625 µA, respectively. The associated equations in Figure 26
can be used to determine the value of RSET.
OPTIONAL
BANDLIMITING
CAPACITOR
AVDD
REFLO
COMP1 AVDD
+1.2V REF
50pF
REFIO
CURRENT
1F
FS ADJ
SOURCE
ARRAY
RSET
IREF
AD9764
VGC
IREF = (1.2–VGC)/RSET
WITH VGC < VREFIO AND 62.5A Յ IREF Յ 625A
Figure 26. Dual-Supply Gain Control Circuit
In some applications, the user may elect to use an external
control amplifier to enhance the multiplying bandwidth,
distortion performance and/or settling time. External amplifiers
capable of driving a 50 pF load such as the AD817 are suitable
for this purpose. It is configured in such a way that it is in
parallel with the weaker internal reference amplifier as shown in
Figure 27. In this case, the external amplifier simply overdrives
the weaker reference control amplifier. Also, since the internal
control amplifier has a limited current output, it will sustain no
damage if overdriven.
EXTERNAL
CONTROL AMPLIFIER
VREF
INPUT
RSET
REFLO
+1.2V REF
REFIO
FS ADJ
AD9764
AVDD
COMP1 AVDD
50pF
CURRENT
SOURCE
ARRAY
Figure 27. Configuring an External Reference Control
Amplifier
ANALOG OUTPUTS
The AD9764 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-end
or differential operation. IOUTA and IOUTB can be converted into
complementary single-ended voltage outputs, VOUTA and
VOUTB, via a load resistor, RLOAD, as described in the DAC
Transfer Function section by Equations 5 through 8. The
differential voltage, VDIFF, existing between VOUTA and VOUTB
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 28 shows the equivalent analog output circuit of the
AD9764 consisting of a parallel combination of PMOS differen-
tial current switches associated with each segmented current
source. The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
and is typically 100 kin parallel with 5 pF. Due to the na-
ture of a PMOS device, the output impedance is also slightly
dependent on the output voltage (i.e., VOUTA and VOUTB) and, to
a lesser extent, the analog supply voltage, AVDD, and full-scale
current, IOUTFS. Although the output impedance’s signal depen-
dency can be a source of dc nonlinearity and ac linearity (i.e.,
distortion), its effects can be limited if certain precautions are
noted.
AD9764
AVDD
IOUTA
RLOAD
IOUTB
RLOAD
Figure 28. Equivalent Analog Output Circuit
IOUTA and IOUTB also have a negative and positive voltage compli-
ance range. The negative output compliance range of –1.0 V is
set by the breakdown limits of the CMOS process. Operation
beyond this maximum limit may result in a breakdown of the
output stage and affect the reliability of the AD9764. The posi-
tive output compliance range is slightly dependent on the full-
scale output current, IOUTFS. It degrades slightly from its nominal
REV. B
–11–

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