AD9806 데이터 시트보기 (PDF) - Analog Devices
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AD9806 Datasheet PDF : 12 Pages
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AD9806
CCD-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = fSHP = fSHD = 18 MHz, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
POWER CONSUMPTION
VDD = 2.7
VDD = 3.0
VDD = 3.3
MAXIMUM CLOCK RATE
65
75
85
18
mW
mW
mW
MHz
CDS
Gain
Allowable CCD Reset Transient1
Max Input Range before Saturation1
0
500
1000
dB
mV
mV p-p
PGA
Gain Control Resolution
Gain Range (See Figure 5a for Gain Curve)
Low Gain (Code 95)2
Max Gain (1023)2
10
Bits
–1
0
+1
dB
32
33
34
dB
BLACK LEVEL CLAMP
Clamp Level (Selected through Serial Interface E-Reg)
CLP0 (E-Reg 00)
32
LSB
CLP1 (E-Reg 01)
48
LSB
CLP2 (E-Reg 10)
64
LSB
CLP3 (E-Reg 11)
16
LSB
SIGNAL-TO-NOISE RATIO3 (@ Low PGA Gain)
74
dB
TIMING SPECIFICATIONS4
Pipeline Delay
Internal Clock Delay5 (tID)
Inhibited Clock Period (tINHIBIT)
Output Delay (tOD)
Output Hold Time (tHOLD)
ADCCLK, SHP, SHD Clock Period
ADCCLK High-Level/Low-Level
SHP, SHD Minimum Pulsewidth
SHP Rising Edge to SHD Rising Edge
9
Cycles
3
ns
10
ns
14.5
16
ns
6
ns
47
55.6
ns
20
28
ns
10
14
ns
20
28
ns
NOTES
1Input signal characteristics defined as follows:
500mV TYP
RESET
TRANSIENT
200mV MAX
OPTICAL
BLACK PIXEL
1V MAX
INPUT
SIGNAL RANGE
2Use equations on page 8 to calculate gain.
3SNR = 20 log10 (Full-Scale Voltage/RMS Output Noise).
420 pF loading; timing shown in Figure 1.
5Internal aperture delay for actual sampling edge.
Specifications subject to change without notice.
REV. 0
–3–
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