AD9806 데이터 시트보기 (PDF) - Analog Devices
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AD9806 Datasheet PDF : 12 Pages
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AD9806–SPECIFICATIONS
AUX-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = 18 MHz, unless otherwise noted.)
Parameter
Min
Typ
Max
POWER CONSUMPTION
Normal (D-Reg 00)
50
High-Speed (D-Reg 01)
95
MAXIMUM CLOCK RATE
Normal (D-Reg 00)
18
High-Speed (D-Reg 01)
28.6
PGA (Gain Selected through Serial Interface F-Reg)
Max Input Range
700
Max Output Range
1000
Gain Control Resolution
7
Gain Range
Min Gain (Code 128)
–2
Max Gain (Code 255)
15
ACTIVE CLAMP
Clamp Level (Selected through Serial Interface E-Reg)
CLP0 (E-Reg 00)
32
CLP1 (E-Reg 01)
48
CLP2 (E-Reg 10)
64
CLP3 (E-Reg 11)
16
TIMING SPECIFICATIONS1
Pipeline Delay
Internal Clock Delay (tID)
Output Delay (tOD)
Output Hold Time (tHOLD)
NOTES
120 pF loading; timing shown in Figure 2.
Specifications subject to change without notice.
9
14.5
16
7
Unit
mW
mW
MHz
MHz
mV p-p
mV p-p
Bits
dB
dB
LSB
LSB
LSB
LSB
Cycles
ns
ns
AUXMID-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = 18 MHz, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
POWER CONSUMPTION
50
mW
MAXIMUM CLOCK RATE
18
MHz
PGA (Gain Selected through Serial Interface F-Reg)
Max Input Range
700
Max Output Range
1000
Gain Control Resolution
9
Gain Range (See Figure 5b for Gain Curve)
Min Gain (Code 512)
–4
Max Gain (Code 1023)
14
mV p-p
mV p-p
Bits
dB
dB
MIDSCALE OFFSET LEVEL (AT MAX PGA GAIN)
462
TIMING SPECIFICATIONS1
Pipeline Delay
Internal Clock Delay (tID)
Output Delay (tOD)
Output Hold Time (tHOLD)
7
NOTES
120 pF loading; timing shown in Figure 2.
Specifications subject to change without notice.
512
562
LSB
9
Cycles
14.5
16
ns
ns
–4–
REV. 0
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