AD9816 데이터 시트보기 (PDF) - Analog Devices
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AD9816 Datasheet PDF : 16 Pages
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AD9816
Table II. 3-Channel Selection
MUX Register Bits
6
5
0
1
1
0
Channel Sequence
Red, Green, Blue
Blue, Green, Red
gain. The gain of the PGA increases linearly as the gain word
increases, and can be calculated by the following equation:
PGA Gain = 1 + (Gain Code/51.2)
where Gain Code varies from 0 to 255. For more information,
refer to the Circuit Descriptions section.
76543210
Table III. 1-Channel Selection
MUX Register Bits
D0 (LSB)
D1
4
3
2
Channel
D2
D3
0
0
1
Red
D4
OBSOLETE 0
1
0
1
0
0
Green
Blue
The offset is variable from –100 mV to +100 mV, and is applied
at the output of the CDS, before the PGA. The resolution is
8 bits, and a sign magnitude coding scheme is used. Table IV
shows the offset voltage that corresponds to the register value.
76543210
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
Figure 9. Offset Registers for Red, Green and Blue
D5
D6
D7 (MSB)
Figure 10. PGA Registers for Red, Green and Blue
Channels
SERIAL TIMING
The 3-wire serial interface timing is shown below. To write to
the AD9816, SLOAD is first taken low. Next, a total of 16 bits
are sent to SDATA, which get latched into the AD9816 on the
rising edges of SCLK. Additional SCLK pulses will be ignored.
The first bit, R/W, should be low to specify a write operation.
The next three bits, A2–A0, are the address bits to specify the
destination register for the data word D7–D0. After all 16 bits
have been clocked, SLOAD is taken high, which internally
latches the data to the appropriate register. The read operation
also starts by taking SLOAD low. First, a one is written to R/W,
to specify a read operation. Next, the three Address Bits A2–A0
Channels
are written to specify the register that will be read. On the 8th
SCLK falling edge, SDATA will begin to output the informa-
Table IV. Offset Adjustment
tion from the desired register. After all eight data bits have been
read, SLOAD is taken back high.
Offset Register
0111 1111 (LSB)
.
.
.
0000 0001
0000 0000
1000 0000
1000 0001
.
.
.
1111 1111
Offset Voltage
+100 mV
.
.
.
+0.8 mV
0.0 mV
0.0 mV
–0.8 mV
.
.
.
–100 mV
R/Wb
SDATA
A2 A1 A0
tDH
tDS
D7 D6 D5 D4 D3 D2 D1 D0
SCLK
tLS
tLH
SLOAD
Figure 11. Write Operation Timing
R/Wb
SDATA
A2 A1 A0
tDH
tDS
D7 D6 D5 D4 D3 D2 D1 D0
tRDV
The PGA is used for correcting color imbalance and for fine
adjustment of the input span before the ADC. Gain is variable
from 1× to 6× (0 dB to 15.5 dB) with 8-bit resolution. An all
“zeros” word (00 . . . 0) corresponds to the minimum gain, and
an all “ones” word (11 . . . 1) corresponds to the maximum
SCLK
SLOAD
tLS
tLH
Figure 12. Read Operation Timing
–10–
REV. A
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