AD9816 데이터 시트보기 (PDF) - Analog Devices
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AD9816 Datasheet PDF : 16 Pages
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DIGITAL SPECIFICATIONS (TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +5.0 V, fADCCLK = 6 MHz,
fCDSCLK1 = 2 MHz, fCDSCLK2 = 2 MHz, CL = 10 pF unless otherwise noted)
AD9816
Parameter
Symbol
Min
Typ
Max
Units
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
3.5
V
VIL
1.0
V
IIH
10
µA
IIL
10
µA
CIN
10
pF
LOGIC OUTPUTS
High Level Output Voltage
VOH
4.5
V
Low Level Output Voltage
VOL
0.1
V
OTIMING BSPECIFICATSIONS OLETE HighLevelOutputCurrent
IOH
Low Level Output Current
IOL
Specifications subject to change without notice.
50
µA
50
µA
(TMIN to TMAX with DVDD = +5.0 V, DRVDD = +5.0 V)
Parameter
Symbol
Min
Typ
CLOCK PARAMETERS
3-Channel Conversion Rate
tCRA
500
1-Channel Conversion Rate
tCRB
160
ADCCLK Pulsewidth
tADCLK
80
CDSCLK1 Pulsewidth
tC1
20
CDSCLK2 Pulsewidth
tC2
60
CDSCLK1 Falling to CDSCLK2 Rising
tC1C2
5
ADCCLK Falling to CDSCLK2 Rising
tADC2
0
CDSCLK2 Falling to ADCCLK Falling
tC2AD
30
Max
Units
ns
ns
ns
ns
2 tADCLK – 30 ns
ns
ns
ns
CDSCLK2 Falling to CDSCLK1 Rising
tC2C1
10
ns
Aperture Delay for CDS Clocks
tAD
10
ns
SERIAL INTERFACE
Maximum SCLK Frequency
fSCLK
10
SLOAD to SCLK Set-Up Time
SCLK to SLOAD Hold Time
tLS
10
tLH
10
SDATA to SCLK Rising Set-Up Time
tDS
10
SCLK Rising to SDATA Hold Time
tDH
10
SCLK Falling to SDATA Valid
tRDV
10
MHz
ns
ns
ns
ns
ns
DATA OUTPUT
Output Delay
tOD
3-State to Data Valid
tDV
Output Enable High to 3-State
tHZ
Latency (Pipeline Delay)
13
15
5
3 (Fixed)
ns
ns
ns
ADCCLK Cycles
REV. A
–3–
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