AD9865 데이터 시트보기 (PDF) - Analog Devices
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AD9865 Datasheet PDF : 48 Pages
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AD9865
SERIAL PORT TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 5.
Parameter
WRITE OPERATION (See Figure 46)
SCLK Clock Rate (fSCLK)
SCLK Clock High (tHI)
SCLK Clock Low (tLOW)
SDIO to SCLK Setup Time (tDS)
SCLK to SDIO Hold Time (tDH)
SEN to SCLK Setup Time (tS)
SCLK to SEN Hold Time (tH)
READ OPERATION (See Figure 47 and Figure 48)
SCLK Clock Rate (fSCLK)
SCLK Clock High (tHI)
SCLK Clock Low (tLOW)
SDIO to SCLK Setup Time (tDS)
SCLK to SDIO Hold Time (tDH)
SCLK to SDIO (or SDO) Data Valid Time (tDV)
SEN to SDIO Output Valid to Hi-Z (tEZ)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min Typ
14
14
14
0
14
0
14
14
14
0
2
Max Unit
32
MHz
ns
ns
ns
ns
ns
ns
32
MHz
ns
ns
ns
ns
14
ns
ns
HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.
Table 6.
Parameter
READ OPERATION1 (See Figure 50)
Output Data Rate
Three-State Output Enable Time (tPZL)
Three-State Output Disable Time (tPLZ)
Rx Data Valid Time (tVT)
Rx Data Output Delay (tOD)
WRITE OPERATION (See Figure 49)
Input Data Rate (1× Interpolation)
Input Data Rate (2× Interpolation)
Input Data Rate (4× Interpolation)
Tx Data Setup Time (tDS)
Tx Data Hold Time (tDH)
Latch Enable Time (tEN)
Latch Disable Time (tDIS)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
II
II
II
II
II
II
II
II
II
II
II
II
Min Typ Max Unit
5
80
MSPS
3
ns
3
ns
1.5
ns
4
ns
20
80
MSPS
10
80
MSPS
5
50
MSPS
1
ns
2.5
ns
3
ns
3
ns
1 CLOAD = 5 pF for digital data outputs.
Rev. A | Page 7 of 48
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