AD9874 데이터 시트보기 (PDF) - Analog Devices

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AD9874

IF Digitizing Subsystem

Analog Devices 

AD9874

PIN CONFIGURATION

48 47 46 45 44 43 42 41 40 39 38 37

MXOP 1

MXON 2

GNDF 3

IF2N 4

IF2P 5

VDDF 6

GCP 7

GCN 8

VDDA 9

GNDA 10

VREFP 11

VREFN 12

PIN 1

IDENTIFIER

AD9874

TOP VIEW

(Not to Scale)

36 GNDL

35 FREF

34 GNDS

33 SYNCB

32 GNDH

31 FS

30 DOUTB

29 DOUTA

28 CLKOUT

27 VDDH

26 VDDD

25 PE

13 14 15 16 17 18 19 20 21 22 23 24

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Description

1 MXOP

2 MXON

3 GNDF

4 IF2N

5 IF2P

6 VDDF

7 GCP

8 GCN

9 VDDA

10 GNDA

11 VREFP

12 VREFN

13 RREF

14 VDDQ

15 IOUTC

16 GNDQ

17 VDDC

18 GNDC

19 CLKP

20 CLKN

21 GNDS

22 GNDD

23 PC

24 PD

25 PE

26 VDDD

Mixer Output, Positive.

Mixer Output, Negative.

Ground for Front End of ADC.

Second IF Input (to ADC), Negative.

Second IF Input (to ADC), Positive.

Positive Power Supply for Front End of ADC.

Filter Capacitor for ADC Full-Scale Control.

Full-Scale Control Ground.

Positive Power Supply for ADC Back End.

Ground for ADC Back End.

Voltage Reference, Positive.

Voltage Reference, Negative.

Reference Resistor: Requires 100 kΩ to

GNDA.

Positive Power Supply for Clock Synthesizer.

Clock Synthesizer Charge Pump Output

Current.

Ground for Clock Synthesizer Charge

Pump.

Positive Power Supply for Clock Synthesizer.

Ground for Clock Synthesizer.

Sampling Clock Input/Clock VCO Tank,

Positive.

Sampling Clock Input/Clock VCO Tank,

Negative.

Substrate Ground.

Ground for Digital Functions.

Clock Input for SPI Port.

Data I/O for SPI Port.

Enable Input for SPI Port.

Positive Power Supply for Internal Digital

Function.

Pin Mnemonic Description

27 VDDH

Positive Power Supply for Digital Interface.

28 CLKOUT Clock Output for SSI Port.

29 DOUTA Data Output for SSI Port.

30 DOUTB

Data Output for SSI Port (Inverted) or

SPI Port.

31 FS

Frame Sync for SSI Port.

32 GNDH

Ground for Digital Interface.

33 SYNCB

Resets SSI and Decimator Counters;

Active Low.

34 GNDS

Substrate Ground.

35 FREF

Reference Frequency Input for Both

Synthesizers.

36 GNDL

Ground for LO Synthesizer.

37 GNDP

Ground for LO Synthesizer Charge Pump.

38 IOUTL

LO Synthesizer Charge Pump Output

Current Charge Pump.

39 VDDP

Positive Power Supply for LO Synthesizer

Charge Pump.

40 VDDL

Positive Power Supply for LO Synthesizer.

41 CXVM

External Filter Capacitor; DC Output of

LNA.

42 LON

LO Input to Mixer and LO Synthesizer,

Negative.

43 LOP

LO Input to Mixer and LO Synthesizer,

Positive.

44 CXVL

External Bypass Capacitor for LNA Power

Supply.

45 GNDI

Ground for Mixer and LNA.

46 CXIF

External Capacitor for Mixer V-I Con-

verter Bias.

47 IFIN

First IF Input (to LNA).

48 VDDI

Positive Power Supply for LNA and Mixer.

–6–

REV. A

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