AD9913(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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AD9913 Datasheet PDF : 32 Pages
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AD9913
Parameter
MISCELLANEOUS TIMING CHARACTERISTICS
Wake-Up Time1
Fast Recovery Mode
Full Sleep Mode
Reset Pulse Width High
DATA LATENCY (PIPELINE DELAY)
Frequency, Phase-to-DAC Output
Frequency-to-DAC Output
Phase-to-DAC Output
Delta Tuning Word-to-DAC Output (Linear Sweep)
CMOS LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS
Logic 1 Voltage
Logic 0 Voltage
POWER SUPPLY CURRENT
DVDD (1.8 V) Pin Current Consumption
DAC_CLK_AVDD (1.8 V)
DAC_AVDD (1.8 V) Pin Current Consumption
PLL_AVDD (1.8 V)
CLK_AVDD (1.8 V) Pin Current Consumption
POWER CONSUMPTION
Single Tone Mode
Modulus Mode
Linear Sweep Mode
Power-Down
Full
Safe
PLL Modes
VCO 1
Differential Input Mode
CMOS Input Mode
Crystal Mode
VCO 2
Differential Input Mode
CMOS Input Mode
Crystal Mode
Conditions/Comments
Matched latency enabled
Matched latency disabled
Matched latency disabled
1 mA load
PLL enabled, CMOS input
PLL disabled, differential input
PLL enabled, XTAL input
PLL disabled
PLL disabled
PLL enabled
Min Typ Max Unit
5
11
11
10
14
1.2
−700
−700
3
1.5
50
57
52
1
SYSCLK cycles2
60 μs
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
V
0.4 V
+700 nA
+700 nA
pF
V
0.125 V
46.5 mA
4.7 mA
6.2 mA
1.8 mA
4.3 mA
66.5 mW
70.5 mW
68.5 mW
94.6 mW
98.4 mW
15 mW
44.8 mW
11 mW
7.5 mW
5.4 mW
15 mW
11.5 mW
9.4 mW
1 Refer to the Power-Down Features section.
2 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier and divider are not used, the
SYSCLK frequency is the same as the external reference clock frequency.
Rev. 0 | Page 4 of 32
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