AD9915 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
AD9915 Datasheet PDF : 47 Pages
| |||
AD9915
Data Sheet
Pin No.
12
18
19
20
21
22
6, 23, 73
7, 17, 24, 74, 84
16, 83
32, 56, 57
33, 35, 37, 38,
44, 46, 49, 51
34, 36, 39, 40,
43, 47, 50, 52,
53, 60
25, 26, 27
28, 29, 30, 31
41
42
45
48
54
55
58
59
61
62
63
64
65
66
Mnemonic
D8/A0
D4/SYNCIO
D3/SDO
D2/SDIO/WR
D1/SCLK/RD
D0/CS/PWD
DVDD (1.8V)
DGND
DVDD_I/O (3.3V)
AVDD (1.8V)
AGND
AVDD (3.3V)
PS0 to PS2
F0 to F3
AOUT
AOUT
DAC_BP
DAC_RSET
REF_CLK
REF_CLK
LOOP_FILTER
REF
SYNC_OUT
SYNC_IN
DRCTL
DRHOLD
DROVER
OSK
I/O1 Description
I/O Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin
acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the
internal registers.
I
Parallel Port Pin/Serial Port Synchronization Pin. This pin is D4 for direct FSK, PSK, or ASK data.
If serial mode is invoked via F0 to F3, this pin resets the serial port.
I/O Parallel Port Pin/Serial Data Output This pin is D3 for direct FSK, PSK, or ASK data. If serial
mode is invoked via F0 to F3, this pin is used for readback mode for serial operation.
I/O Parallel Port Pin/Serial Data Input and Output/Write Input. This pin is D2 for direct FSK, PSK,
or ASK data. If serial mode is invoked via F0 to F3, this pin is used for the SDIO for serial
operation. If parallel mode is enabled, this pin writes to change the values of the internal
registers.
I
Parallel Port Pin/Serial Clock/Read Input. This pin is D1 for direct FSK, PSK, or ASK data. If serial
mode is invoked via F0 to F3, this pin is used for SCLK for serial operation. If parallel mode is
enabled, this pin reads back the value of the internal registers.
I
Parallel Port Pin/Chip Select/Parallel Width. This pin is D0 for direct FSK, PSK, or ASK data. If
serial mode is invoked via F0 to F3, this pin is used for the chip select for serial operation. If
parallel mode is enabled, this pin sets either 8-bit data or 16-bit data.
I
Digital Core Supplies (1.8 V).
I
Digital Ground.
I
Digital Input/Output Supplies (3.3 V).
I
Analog Core Supplies (1.8 V).
I
Analog Ground.
I
Analog DAC Supplies (3.3 V).
I
Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight
phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the
current contents of all input/output buffers to the corresponding registers. State changes
must be set up on the SYNC_CLK pin (Pin 82).
I
Function Pins. Digital inputs. The state of these pins determines if a serial or parallel interface
is used. In addition, the function pins determine how the 32-bit parallel data-word is
partitioned for FSK, PSK, or ASK modulation mode.
O DAC Complementary Output Source. Analog output (voltage mode). Internally connected
through a 50 Ω resistor to AVDD (3.3 V).
O DAC Output Source. Analog output (voltage mode). Internally connected through a 50 Ω
resistor to AVDD (3.3 V).
I
DAC Bypass Pin. Provides access to the common control node of the DAC current sources.
Connecting a capacitor between this pin and ground can improve noise performance at the
DAC output.
O Analog Reference. This pin programs the DAC output full-scale reference current. Connect a
3.3 kΩ resistor to AGND.
I
Complementary Reference Clock Input. Analog input.
I
Reference Clock Input. Analog input.
O External PLL Loop Filter Node.
O Local PLL Reference Supply. Typically at 2.05 V.
O Digital Synchronization Output. The pin synchronizes multiple chips.
I
Digital Synchronization Input. The pin synchronizes multiple chips.
I
Ramp Control. Digital input (active high). This pin controls the sweep direction (up/down).
I
Ramp Hold. Digital input (active high). Pauses the sweep when active.
O Ramp Over. Digital output (active high). This pin switches to Logic 1 when the digital ramp
generator reaches the programmed upper or lower limit.
I
Output Shift Keying. Digital input (active high). When the OSK features are placed in either
manual or automatic mode, this pin controls the OSK function. In manual mode, it toggles
the multiplier between 0 (low) and the programmed amplitude scale factor (high). In
automatic mode, a low sweeps the amplitude down to zero and a high sweeps the amplitude
up to the amplitude scale factor.
Rev. F | Page 10 of 47
Share Link: 