AD9956YCPZ-REEL 데이터 시트보기 (PDF) - Analog Devices
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AD9956YCPZ-REEL Datasheet PDF : 32 Pages
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AD9956
SPECIFICATIONS
AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± 5% (@ TA = 25°C) DAC_RSET = 3.92 kΩ, CP_RSET = 3.09 kΩ,
DRV_RSET = 4.02 kΩ, unless otherwise noted.
Table 1.
Parameter
Min
RF DIVIDER (REFCLK ) INPUT SECTION (÷R)
RF Divider Input Range
1
Input Capacitance (DC)
Input Impedance (DC)
Input Duty Cycle
42
Input Power/Sensitivity
−10
Input Voltage Level
350
PHASE FREQUENCY DETECTOR/CHARGE PUMP
PLLREF Input
Input Frequency2
÷M Set to Divide by at Least 4
÷M Bypassed
Input Voltage Levels
200
Input Capacitance
Input Resistance
PLLOSC Input
Input Frequency
÷N Set to Divide by at Least 4
÷N Bypassed
Input Voltage Levels
200
Input Capacitance
Input Resistance
Charge Pump Source/Sink Maximum Current
Charge Pump Source/Sink Accuracy
−15
Charge Pump Source/Sink Matching
−5
Charge Pump Output Compliance Range3
0.5
PLL_LOCK Drive Strength
PHASE FREQUENCY DETECTOR NOISE FLOOR
@ 50 kHz PFD Frequency
@ 2 MHz PFD Frequency
@ 100 MHz PFD Frequency
@ 200 MHz PFD Frequency
CML OUTPUT DRIVER (DRV)
Differential Output Voltage Swing4
Maximum Toggle Rate
655
Common-Mode Output Voltage
Output Duty Cycle
42
Output Current
Continuous5
Rising Edge Surge
Falling Edge Surge
Output Rise Time
Typ Max
2700
3
1500
50
58
+4
1000
Unit
MHz
pF
Ω
%
dBm
mV p-p
Test Conditions/Comments
DDS SYSCLK not to exceed
400 MSPS
Single-ended, into a 50 Ω load1
655
200
450 600
10
1500
MHz
MHz
mV p-p
pF
Ω
450
1500
2
655
200
600
10
4
+5
+5
CP_VDD − 0.5
MHz
MHz
mV p-p
pF
Ω
mA
%
%
V
mA
149
dBc/Hz
133
dBc/Hz
116
dBc/Hz
113
dBc/Hz
720
mV
MHz
1.75
V
50 58
%
7.2
mA
20.9
mA
13.5
mA
250
ps
50 Ω load to supply, both lines
100 Ω terminated, 5 pF load
Rev. B | Page 4 of 32
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