ADC0804S040 데이터 시트보기 (PDF) - NXP Semiconductors.
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ADC0804S040 Datasheet PDF : 19 Pages
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NXP Semiconductors
ADC0804S030/040/050
Single 8 bits ADC, up to 30 MHz, 40 MHz or 50 MHz
Table 6. Characteristics
VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V;
VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 °C to 70 °C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V, Vi(a)(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vref(dif)
differential reference
voltage
VRT − VRB
2.0
2.37
3.0
V
Iref
reference current
VRT − VRB = 2.37 V
-
Rlad
ladder resistance
-
TCRlad
ladder resistor
-
temperature coefficient
9.7
-
245
-
456
-
mA
Ω
mΩ/K
Voffset
Vi(a)(p-p)
offset voltage
peak-to-peak analog
input voltage
BOTTOM;
VRT − VRB = 2.37 V
TOP; VRT − VRB = 2.37 V
[2] -
[2] -
[3] 1.7
175
-
mV
175
-
mV
2.02
2.55
V
Digital outputs D7 to D0 and IR (referenced to OGND)
VOL
LOW-level output
IOL = 1 mA
voltage
0
-
0.5
V
VOH
HIGH-level output
IOH = − 1 mA
voltage
VCCO − 0.5 -
VCCO
V
Io
output current
in 3-state mode;
0.5 V < VO < VCCO
Switching characteristics; Clock input CLK; see Figure 4[1]
−20
-
+20
µA
fclk(max)
maximum clock
frequency
ADC0804S030TS
ADC0804S040TS
30
-
-
MHz
40
-
-
MHz
ADC0804S050TS
50
-
-
MHz
tw(clk)H
HIGH clock pulse width full effective bandwidth
8.5
-
-
ns
tw(clk)L
LOW clock pulse width full effective bandwidth
5.5
-
-
ns
Analog signal processing
Linearity
INL
integral non-linearity fclk = 40 MHz; ramp input
-
DNL
differential non-linearity fclk = 40 MHz; ramp input
-
Eoffset
offset error
middle code; VRB = 1.3 V;
-
VRT = 3.67 V
EG
gain error
from device to device;
[4] -
VRB = 1.3 V; VRT = 3.67 V
Bandwidth (fclk = 40 MHz)
B
bandwidth
full-scale sine wave
[5] -
±0.2
±0.5
LSB
±0.12 ±0.22
LSB
±0.25 -
LSB
±0.1
-
%
15
-
MHz
75 % full-scale sine wave
-
20
-
MHz
ts(LH)
LOW to HIGH settling
time
small signal at mid-scale;
-
VI = ±10 LSB at code 512
full-scale square wave; see [6] -
Figure 6
350
-
1.5
3.0
MHz
ns
ts(HL)
HIGH to LOW settling
time
-
1.5
3.0
ns
ADC0804S030_040_050_2
Product data sheet
Rev. 02 — 14 August 2008
© NXP B.V. 2008. All rights reserved.
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