EVAL-ADCMP572BCPZ(RevB) 데이터 시트보기 (PDF) - Analog Devices
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EVAL-ADCMP572BCPZ Datasheet PDF : 14 Pages
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ADCMP572/ADCMP573
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VTP 1
VP 2
VN 3
VTN 4
ADCMP572
ADCMP573
TOP VIEW
12 VCCO
11 Q
10 Q
9 VCCO
Data Sheet
NOTES
1. LEAVE EPAD FLOATING UNLESS IMPROVED THERMAL OR MECHANICAL
STABILITY IS DESIRED, IN WHICH CASE SOLDER IT TO THE APPLICATION BOARD.
Figure 2. ADCMP572/ADCMP573 Pin Configuration
Table 3. Pin Function Descriptions
Pin
No. Mnemonic Description
1
VTP
2
VP
3
VN
4
VTN
5, 16 VCCI
Termination Resistor Return Pin for VP Input.
Noninverting Analog Input.
Inverting Analog Input.
Termination Resistor Return Pin for VN Input.
Positive Supply Voltage for Input Stage.
6
LE
Latch Enable Input Pin, Inverting Side.
In compare mode (LE = low), the output tracks changes at the input of the comparator.
In latch mode (LE = high), the output reflects the input state just prior to the comparator’s being placed into latch
mode. LE must be driven in complement with LE.
7
LE
Latch Enable Input Pin, Noninverting Side.
In compare mode (LE = high), the output tracks changes at the input of the comparator.
In latch mode (LE = low), the output reflects the input state just prior to the comparator’s being placed into latch
mode. LE must be driven in complement with LE.
8
VCCO/VTT
Termination Return Pin for the LE/LE Input Pins.
For the ADCMP572 (CML output stage), this pin is internally connected to and also should be externally connected
to the positive VCCO supply.
For the ADCMP573 (RSPECL output stage), this pin should normally be connected to the VCCO – 2 V termination
potential.
9, 12 VCCO
13, 15 GND
Positive Supply Voltage for the CML/RSPECL Output Stage.
Ground.
10
Q
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog
voltage at the inverting input, VN, provided the comparator is in compare mode. See the LE/LE descriptions (Pins 6
and 7) for more information.
11
Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input VP is greater than the analog
voltage at the inverting input, VN, provided the comparator is in compare mode.
See the LE/LE descriptions (Pins 6 and 7) for more information.
14
HYS
Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a suitably sized
resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of RHYS hysteresis control
resistor.
Isolated
Heat Sink
The metallic back surface of the package is not electrically connected to any part of the circuit, and it can be left
floating for best electrical isolation between the package handle and the substrate of the die. However, it can be
soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal at
package corners is connected to the heat sink paddle.
EPAD
Exposed Pad. Leave EPAD floating unless improved thermal or mechanical stability is desired, in which case solder
it to the application board.
Rev. B | Page 6 of 14
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