ADCMP580(RevB) 데이터 시트보기 (PDF) - Analog Devices
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ADCMP580 Datasheet PDF : 16 Pages
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Data Sheet
ADCMP580/ADCMP581/ADCMP582
TIMING INFORMATION
Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the
terms shown in Figure 2.
LATCH ENABLE
LATCH ENABLE
tS
tPL
tH
50%
DIFFERENTIAL
VN
INPUT VOLTAGE
VOD
VN ± VOS
Q OUTPUT
Q OUTPUT
tPDL
tPLOH
50%
tPDH
tF
50%
tPLOL
tR
Figure 2. Comparator Timing Diagram
Table 2. Timing Descriptions
Symbol Symbol Description
tPDH
Input-to-Output High Delay
tPDL
Input-to-Output Low Delay
tPLOH
Latch Enable-to-Output High Delay
tPLOL
Latch Enable-to-Output Low Delay
tH
Minimum Hold Time
tPL
Minimum Latch Enable Pulse Width
tS
Minimum Setup Time
tR
Output Rise Time
tF
Output Fall Time
VN
Normal Input Voltage
VOD
Voltage Overdrive
Timing Description
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output high-to-low transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
Minimum time that the latch enable signal must be high to acquire an input signal change.
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
Difference between the input voltages VP and VN for output true.
Difference between the input voltages VP and VN for output false.
Rev. B | Page 5 of 16
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