ADG2128WBCPZ-REEL7 데이터 시트보기 (PDF) - Analog Devices

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ADG2128WBCPZ-REEL7

I2C® CMOS 8 × 12 Unbuffered Analog Switch Array With Dual/Single Supplies

Analog Devices 

ADG2128

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Data Sheet

32 31 30 29 28 27 26 25

VSS 1

NC 2

PIN 1

INDICATOR

24 VDD

23 NC

X0 3

X1 4

X2 5

X3 6

ADG2128

12 × 8

TOP VIEW

(Not to Scale)

22 X11

21 X10

20 X9

19 X8

X4 7

18 X7

X5 8

17 X6

9 10 11 12 13 14 15 16

NOTES

1. THE EXPOSED PADDLE IS SOLDERED TO VSS.

2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions1

Pin No. Mnemonic Description

1

VSS

2, 23

NC

Negative Power Supply in a Dual-Supply Application. For single-supply applications, this pin should be tied to GND.

This pin is not connected internally (see Figure 3).

3 to 8, X0 to X11

17 to 22

Can be inputs or outputs.

9 to 16 Y0 to Y7

Can be inputs or outputs.

24

VDD

25

VL

26

SDA

Positive Power Supply Input.

Logic Power Supply Input.

Digital I/O. Bidirectional open drain data line. External pull-up resistor required.

27

SCL

Digital Input, Serial Clock Line. Open drain input that is used in conjunction with SDA to clock data into the

device. External pull-up resistor required.

28

A0

Logic Input. Address pin that sets the least significant bit of the 7-bit slave address.

29

A1

Logic Input. Address pin that sets the second least significant bit of the 7-bit slave address.

30

A2

Logic Input. Address pin that sets the third least significant bit of the 7-bit slave address.

31

RESET

Active Low Logic Input. When this pin is low, all switches are open, and appropriate registers are cleared to 0.

32

GND

Ground Reference Point for All Circuitry on the ADG2128.

EPAD

Exposed Pad. The exposed paddle is soldered to VSS.

1 It is recommended that the exposed paddle be soldered to VSS to improve heat dissipation and crosstalk.

Rev. D | Page 10 of 28

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