ADG633(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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ADG633
(Rev.:Rev0)

CMOS ±5 V/+5 V/+3 V Triple SPDT Switch

Analog Devices 

OUTLINE DIMENSIONS

16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

5.10

5.00

4.90

16

9

4.50

4.40

4.30

6.40

BSC

1

8

PIN 1

1.20

MAX

0.15

0.20

0.05

0.09

0.75

0.30

8

0.60

0.65

BSC

0.19

COPLANARITY

SEATING

PLANE

0

0.45

0.10

COMPLIANT TO JEDEC STANDARDS MO-153AB

16-Lead Frame Chip Scale Package [LFCSP]

4 mm  4 mm Body

(CP-16)

Dimensions shown in millimeters

4.0

BSC SQ

0.60 MAX

0.60 MAX

PIN 1

INDICATOR

PIN 1

INDICATOR

TOP

VIEW

12 MAX

1.00 MAX

0.65 NOM

1.00

0.90

0.38

0.80

0.30

SEATING

PLANE

0.23

3.75

BSC SQ

0.65 BSC

0.75

0.55

0.35

13

12

16

1

BOTTOM

VIEW

9

4

2.25

8

5

1.70 SQ

0.75

1.95 BSC

0.05 MAX

0.02 NOM

0.20 REF COPLANARITY

0.08

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

ADG633

REV. 0

–11–

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